Hi team,
My customer is wondering why the LOCK pin would have a pulse before the PDB is pull up.
I will send the schematic later, but could you share you ides of this kind of behaviour?
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Hi team,
My customer is wondering why the LOCK pin would have a pulse before the PDB is pull up.
I will send the schematic later, but could you share you ides of this kind of behaviour?
Hello James,
Can you please verify the power sequence for the VDD33, VDDIO, VDD12, and PDB match the sequence diagram in section 9.2 of the 948 datasheet?
Best Regards,
Casey