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DS90UB940N-Q1: DS90UB940N-Q1: CSI-2 indirect registers map for FS and FE settings or tLPX(Frame Gap register settings)

Part Number: DS90UB940N-Q1


Hello TI

My customer project uses your DS90UB940 as a deserializer for AVM.
While debugging, I got a black screen.
After reviewing the datasheet and technical review again, the MIPI_TX waveform timing for the 940 shows that
It turns out that the LPS time between FE and FS is very short.
Therefore, as shown in the figure below, the LPS time can be adjusted to the power of 1 to 2 ^15tPLX.
Can you please tell me how to adjust these times?

I have to change the settings for Frame Start and Frame End timings, I know that they can be changed by the 0x0C and 0x0D Frame Gap registers , I'd like to know what are individual bits in these registers responsible for to set optimal values.

However,I did not find the introduction of Frame Gap Register in the data sheet. 0x0C and 0x0D are not the address of this register

Please tell me where the register is to set the Frame Gap register.

  • Hello Zhang,

    Monday is a US holiday and we will be returning to the office on Tuesday 9/8. Thank you for your patience 

    Best Regards,

    Casey 

  • Hi, 

    It sounds you forget attaching the figures?

    yes, the timeslot between FS and FE can be fine tuned, this is indirect reg.0x0c/0x0d. 0x0d is FRAME_GAP[15:8],  and 0x0c is FRAME_GAP[7:0]. both these are read/written through reg. 0x6c/0x6d.

    write 0x0d to 0x6c

    write 0x10 to 0x6d

    with above operation, the reg. FRAME[15:0] is changed from default 0x00 "short" to 0x1000 (2<11tPLX).

    regards,

    Steven