DS90UB948-Q1: DS90UB948-Q1 PCB LAYOUT REVIEW

Zhanpeng Li

Intellectual 2140 points

Part Number: DS90UB948-Q1

Hi team,

could you help review the schemtic and pcb layout of DS90UB948-Q1?

attached the schemtic and PCB below:
CLUSTER-948LAYOUT.rar IVI-948layout.rar

Brandon.

over 4 years ago

0 Zhanpeng Li over 4 years ago

TI__Intellectual 2140 points

add IVI layout below:
3652.IVI-948layout.rar

0 Casey McCrea over 4 years ago in reply to Zhanpeng Li

TI__Guru** 103215 points

Hello Zhang,

Monday is a US holiday and we will be returning to the office on Tuesday 9/8. Thank you for your patience

Best Regards,

Casey

0 Steven(Shenzhen) Shi over 4 years ago in reply to Zhanpeng Li

TI__Mastermind 30515 points

hi,

1. the sch. design sounds good, it follows up ti's recommended applcation.

2. for layout, pls check some comments as below

a. fpd-link channnel: why not put both channels' in the bottom layer to reduce the stub? b. the high speed trace can be far away from the 3.3V supplies. c. the AC coupling sounds to be 0603 package? pls use 0402.

b. for lvds channel, pls be careful of the crosstalk between lvds signal and supplies.

regards,

Steven

0 michaux over 4 years ago in reply to Steven(Shenzhen) Shi

Prodigy 60 points

Thanks for your comments. I have a few questions.

1.Can we remove the common mode inductance on the 948FPDLINK?

2.a. Maybe we can only put one channel at the bottom layer, because there is a wiring problem with the connector position when two channels are on the same layer, as shown as the blue circle belown:

b.the high speed trace can be far away from the 3.3V supplies.

b. for lvds channel, pls be careful of the crosstalk between lvds signal and supplies.

----I don't quite understand this point, is it that the power supply of layer 5 cannot pass under FPDLINK or LVDS?

c.yes,the AC coupling capacitances are 0603 package,because the 50V 100NF capacitance in our database is only 0603package, 0402 100NF is 16v.

Or, can we use a 50V 33NF AC capacitor at 948 FPDLINK when 941FPDLINK AC capacitance is 100NF?

0 Steven(Shenzhen) Shi over 4 years ago in reply to michaux

TI__Mastermind 30515 points

1. CMC is helpful for system level EMC design. For FPD-Link chip-level operation, this CMC is not needed. so if your system EMC design is robust, you can remove it.

2.a. you can refer to TI's EVM design, it has layout example.

2.b. the high speed signal via is close to the supply

2.c, it is popular for 0402 package capcitor with 50V rating (auto grade), if the back channel rate is 20Mbps, you can use 0.033uF cap.

regards,

Steven

0 Zhanpeng Li over 4 years ago in reply to Steven(Shenzhen) Shi

TI__Intellectual 2140 points

Hi team

update the picture below:

Brandon

0 Steven(Shenzhen) Shi over 4 years ago in reply to Zhanpeng Li

TI__Mastermind 30515 points

Yes this i better. you also can put them in the bottom layer.

regards,

Steven

0 michaux over 4 years ago in reply to Steven(Shenzhen) Shi

Prodigy 60 points

hi,steven

Our products use vertical connectors, which are different from the EVM design. The SI simulation of the following wiring shows that impedance continuity is problematic.

Therefore, according to the simulation results and Suggestions, the routing of FPDLINK in the current test board is changed to fan out from the first and fourth layers, as shown in the figure below.

Is it better for FPDLINK to fan out from the fourth and sixth floors or the fifth and sixth floors?

0 Steven(Shenzhen) Shi over 4 years ago in reply to michaux

TI__Mastermind 30515 points

In you TDR simulation, you can improve the trace to make the impedance controlling well.

If you simulate the total trace including HSD PAD and cable together, it is better you can put them in the bottom layer.

regarsd,

Steven

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DS90UB948-Q1: DS90UB948-Q1 PCB LAYOUT REVIEW