hi ti
should I enable DSI_CONTINUOUS_CLK bit on 0x4f register when using split mode? Now we using DSI reference clock(BRIDGE_CFG2 = 0x80)
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hi ti
should I enable DSI_CONTINUOUS_CLK bit on 0x4f register when using split mode? Now we using DSI reference clock(BRIDGE_CFG2 = 0x80)
Hello,
If you are using DSI reference clock mode, then the DSI clock needs to be continuous. It is not related to split mode. Also the DSI_CONTINUOUS_CLOCK bit is automatically set by the MODE_SEL strapping
Best Regards,
Casey
hi Casey
thanks for your reply.
Should we set up the DSI clock to CONTINUOUS on SOC side?
Now we occur a issue that when we write 0x0c to 0x4f register on 941, the screen can show video normally. but if we write 0x8c to 0x4f register on 941,In most of the cases, the screen can't show anything.
Hello,
Yes, the DSI clock should be set for continuous on the SoC side. But also note that the 0x4F[7] bit works as follows:
0x4F[7] = 1 -> Discontinuous Clock
0x4F[7] = 0 -> Continuous Clock
So your configuration of 0x0C is correct for this application. We will be making this more clear in the next datasheet update
Best Regards,
Casey
hi Casey
Many thanks for you reply.
now i was confuse by your suggestion and my test result.
For my test result:
After I set up DSI's clock as continuous mode(HS mode)on SOC side, and write 0x8c to 0x4f register on 941, now the screen can show video every time.
For your suggestion:
0x4F[7] = 1 -> Discontinuous Clock
0x4F[7] = 0 -> Continuous Clock
So I think that is hard to understand, SOC's DSI Continuous clock work well with 941's Discontinuous.
Could you please help to double confirm that?
Hello,
Yes, apologies I noticed this was incorrect so I'll revise my previous statement.
0x4F[7] = 1 -> Continuous Clock
0x4F[7] = 0 -> Discontinuous Clock
It sounds like this also resolved your issue!
Best Regards,
Casey