Hi,
I have a question when using TLK1221.
The pin configuration is as follows：
My test program: Send a group of data every 1ms, which is AABBCCDD+COUNT, COUNT is a counter value from 0 to 255, and send x"BC"(K28.5) when idle.
When send data, I use PrSl_RefClk_s; when receive data, I use TLK_RBC0.
1) when I enable loop fuction, thus TLK_LOOPEN <= '1', The data received is correct.
PrSv_EncDin_s is the data to be sent, TLK_TD_F is the 8b/10b encoded data sent to TLK1221; TLK_RD_F is the received data of TLK1221, which is sent to the FPGA, and dout is the decoded data. The following figure shows that the sending and receiving are consistent.
The sampling clock of SignalTap is the output clock RBC0 of TLK.
2) Connect J3/J4 with a SATA cable, the blue is the count value, sometimes correct, sometimes wrong. The first 4 data received are fixed to 555B333D.
When using one card for sending and another card for receiving, the problem remains the same.
3) The schematic is as follows, please help analyze, thank you!
