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DS90UB947-Q1: quesitons about 947/948

Betty Guo
Expert 7300 points
Part Number: DS90UB947-Q1

Hi team,

customer's display only have 1channel LVDS input, the resolution is 1920*720, clock of LVDS is 85MHz(typ) ~104MHz(max)

they would like to use 947&948 in this project,and have below solution:

1. CPU output 1-lane LVDS  to 947 /948, then output 1channel LVDS to display

2. CPU outptu 2-lane LVDC to 947/948, then output 1channle LVDS to display

the questions as below:

(1) which solution is recommended in this case? Can 947/948  be used in solution 2? 

(2) For  solution 1, since the clock 85MHz(type) is in the range of 947/948 CLK, but the max is not. we have concern about this

(3) The register of 0x49  FPD_TX_MODE can set the outptu mode.Can we use this register to set the signle output or Dual?

(4) Generally, what distance can be transmitted through FPD line?

thanks.

  • 0
    TI__Genius 12866 points

    Hi Betty,

    The Typ to Max PCLK you have is on the edge of 1 lane LVDS limitation. With 1 lane, we can support up to 96MHz. 

    1. If 104MHz is needed, option 2 is the only possible case.

    2. Typically, the PCLK is running at a fixed value. If the display can handle 85MHz typ, you can verify with the display vendor and possibly run at fixed 85MHz.

    3. Yes, this controls the 948 single/dual OLDI output

    4. This would depend on the cable, connector, and PCB quality. Please see 948 datasheet section 7.3.12.1 Transmission Distance

    Best Regards,

    Charley Cai

  • 0 in reply to Charley Cai
    TI__Expert 7300 points

    thanks Charley.

    one more question about clock.

    In the datasheet of 948 about 2-lane input, single link output. the CLK1 will be the twice the rate as PCLK.Does the clock need to be configured by the customer or can the device be automatically detected?

    thanks. 

  • 0 in reply to Betty Guo
    TI__Genius 12866 points

    Hi Betty,

    Once you set 948 into 2 lane input, single oldi output mode, the clock will be configured by the device. The customer do not need to adjust the source PCLK.

    Best Regards,

    Charley Cai

  • 0 in reply to Charley Cai
    TI__Expert 7300 points

    got it, thanks Charley.