TMDS442: electrical stress of TMDS442 at power off

Akihisa Tamazaki

Part Number: TMDS442

Hello team,

The customer would like to know the electric stress in the following case.

In the power saving mode, the Reciever Board (TMDS442) is powered off, but the Source board remain power on. So the VIDEO signal and +5V/DDC are output to the reciever board (TMDS442) .
Is there any problem in terms of electrical stress?

When the power off, is the TMDS442source side (+5V_PWR, SCL/SDA, A/B*) Hi-Z?

Your help would be so appreciated.

Best Regards,
Akihisa Tamazaki

over 5 years ago

0 David (ASIC) Liu over 5 years ago

TI__Guru**** 177926 points

Tamazaki-san

Please refer to this table. I would gate the 5V_PWR on the receiver board.

Thanks

David

0 Akihisa Tamazaki over 5 years ago in reply to David (ASIC) Liu

TI__Genius 12460 points

David-san,

Thank you for your comment.

The customer would like to confirm the electrical stress and status when Vcc(3.3V) is powered off although source IC is powered on?. Would you please advise about below?

1) Is there any problem with all I/Os of TMDS422 in terms of electrical stress when Vcc(3.3V) is powered off although source IC is powered on?

2) is the TMDS source side (+5V_PWR, SCL/SDA, A/B*) Hi-Z when Vcc(3.3V) is powered off?

Best Regards,
Akihisa Tamazaki

0 David (ASIC) Liu over 5 years ago in reply to Akihisa Tamazaki

TI__Guru**** 177926 points

Tamazaki-san

The TMDS442 input pins do not incorporate the failsafe circuits, so I would not drive it when VCC is off.

This goes back to my previous response that 5V_PWR should be gated. When 5V_PWR is L, HPD is low and SDA/SCL, Y/Z are in High-Z state. When the source sees the HPD being low, the source should not drive the SCL/SDA and A/B per the HDMI spec even when it is powered on.

Thanks

David

0 Akihisa Tamazaki over 5 years ago in reply to David (ASIC) Liu

TI__Genius 12460 points

David-san.

Thank you for your advice.

Best Regards,
Akihisa Tamazaki

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TMDS442: electrical stress of TMDS442 at power off