TCAN4550-Q1: TCAN4550 Question for new project design

Hi Songzhen,

1. For the Absolute Maximum Ratings, such as max supply voltage=  42V. Is there any time limited for this data?

No, we do not have any time limit specifications associated with the Absolute Maximum Ratings.  However, these ratings such as the 42V max supply voltage are intended to be for tolerance of transient voltages and not a steady state operating voltage.

2. In page 5 of datasheet(Chapter 6.6). There is a current data. What's the supply voltage?

The Supply Characteristics Table specifies the maximum Isup current across a range of Supply Voltages.  Data was collected and aggregated for the following voltages to make these specifications 5.5V, 12V, 24V, and 30V.

3. For the page 6 of datasheet(Chapter 6.6), when the Vio= 5V, it shows the Ivio data. Could we provide this data under Vio =3.3V?

Many factors go into the determination of the datasheet limits for a specific set of test conditions.  I don't think we can provide a specific datasheet limit or the 3.3V case at this time, but I could look into data that was collected for this parameter and give some more specific values for informational purposes only.  I think that is what you are asking and if so let me know.  But if an official datasheet update for 3.3V data is needed, this is a much more significant request that would require some consideration from the product line before agreeing to provide that update.

4. When we connect a external crystal. What's the frequency requirement? Is it between 20~40Mhz? Does it have PPM over temperature requirement?

The clocking requirements are more related to the ISO CAN Standard requirements. In order to maintain standard bit timing and communication baud rates, CAN clock frequencies are typically 20Mhz, 40Mhz, or 80Mhz which allow the standard rates to be supported across the industry.  However, the TCAN4550 was designed to support the 20Mhz and 40Mhz clock frequencies while meeting all of the timing specifications in the datasheet.  However, it was not designed to operate from an 80Mhz clock which is needed for support of higher CAN FD Data rates and therefore it has not been characterized with a clock faster than 40Mhz.

Table frequency tolerance is also based on the CAN Standards at +/- 0.5%, but this too may be system dependent because the margin of clock is relative to the clock frequency of other nodes on the bus.  It is assumed that all notes are within the same tolerance, but there could be other factors that reduce the timing tolerance requirements such as the required data rate.  Faster Data rates may need a tighter tolerance specification because of fewer clock pulses per data bit period as compared to slower data rates where there are many clock pulses (or time quanta) er each CAN FD data bit period. However, this is not really a device requirement and is more of a system level requirement.

The TCAN4550 has based it's timer settings based on either a 20Mhz or 40Mhz clock with +/-0.5% frequency tolerance.  However, outside of that the TCAN4550 will work with any other clock frequency with the only understanding that these timer values will have to be scaled according to the actual frequency used. 

Finally, it should be noted that not all clock frequencies are tolerated in most CAN applications due to the need for an Integer number of Time Quanta or clock cycles per bit period.  For example, an 1Mbps bit rate at a 20Mhz clock frequency would give you 20 time quanta per bit period.  If you used a 32.768Mhz crystal, then you would have 32.768 time quanta per bit time and that is not an integer value which will result in either a bit period with 32 or 33 time quanta and this will result in a phase error for messages transmitted to other nodes on the bus that are using a standard value.

A 45% to 55% duty cycle is also a specification in the Electrical Characteristics of the datasheet.

Also, the datasheet specifies a maximum crystal ESR of 60 ohms to certify that the internal Pierce Oscillator can properly establish oscillation in the application.  However, most other specifications are left to the crystal and system requirements on what is suitable and what is not.

5. When INH(15)、WAKE(12)、NWKPQ(2) is unused, how to deal with it?

When INH is not used, it can be left floating (section 8.3.5 of the datasheet).

When WAKE is not used, it can be tied directly to Vsup or GND.  (section 8.3.6 of the datasheet).

When the nWKRQ pin is unused, it can be left floating because it is an output pin.  Generally any unused output pin can be left floating but unused input pins should never be left floating and need to be tied high or low either directly or through a current limiting resistor.

Let me know if you have any additional questions and what your expectation or question #3 is, and I will follow up accordingly.

Regards,

Jonathan