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DP83867E: SGMII mode 4 strapping

Obinna Ezeilo
Intellectual 2385 points
Part Number: DP83867E

Hi Team, 

A customer of mine is using the the DP83867ERGZT PHY for a project and needed some clarification on the SGMII mode implementation. 

Currently they have implemented multiple PHY's in SGMII mode. Some of the PHY's are strapped with mode 4 on the RX_D0, RX_D1, RX_D2 and RX_D3 pins. According to the datasheet (page 37) this is done with Rhi=2k49 and Rlo=Open. Now there is also a note stating the following: "For SGMII Mode4 strap, TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1, RX_D2 and RX_D3" (see the screenshot image below). They've tried, but can't seem to understand why this is recommended.

Could you elaborate on this? Does it not work when Rhi is set to 2k49 and Rlo is left open?

Thanks in advance for the support. 

BR, 

Obinna. 

  • 0
    TI__Expert 7040 points

    Hi Obinna,

    The note that "TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1, RX_D2 and RX_D3" has to do with the SGMII signals on these pins in SGMII mode. We recommend Rhi = 4 kΩ and Rlo = 10 kΩ to maintain a common mode about voltage of ~VDDIO/2. Note this only applies when the RX data pins are set in SGMII mode. Using the strap resistors in Table 5 will still work as expected to strap the device into the correct mode, we just provide a solution for SGMII operation specifically as well. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Intellectual 2385 points

    Hi Justin, 

    So if the PHY is used in SGMII mode will it work when Rhi is set to 2K49 and Rlo is left open?

    Thanks for the support. 

    Obinna. 

  • 0 in reply to Obinna Ezeilo
    TI__Expert 7040 points

    Hi Obinna,

    Yes, the PHY will strap into the correct mode but the signal integrity of the SGMII path will be better if the SGMII recommended strap settings are used.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Intellectual 2385 points

    Hi Justin, 

    One more thing, with 4K and 10K the mode 4 minimum voltage is not met. According to table 5, "mode 4" should have a minimum voltage of 0.694 x VDDIO. 

    Are there other minimal voltage requirements for mode 4 in SGMII mode? The customer wants to to limit the amount of different resistors on their design. THey already have a 4K43 ohms (1%) and a 10K ohms (1%) resistor in the design. Is it allowed to use 4K43 ohms value for strapping mode 4? 

    VDDIO calculations with internal 9K resistance:

    • With a 4K resistor: 9k//10K = 4.73K -> 4.73K/(4.73K + 4K)= 0.543 x VDDIO
    • With a 4k43 resistor: 9k//10K = 4.73K -> 4.73K/(4.73K + 4.43K)= 0.518 x VDDIO

    Thanks and looking forward to your response.

    KR, 

    Obinna. 

  • 0 in reply to Obinna Ezeilo
    TI__Expert 7040 points

    Hi Obinna, 

    Please use a 4kOhm pull-up resistor. This configuration has been validated over the acceptable voltage and temperature specifications of the device. Increasing the R_hi value would require the customer to validate it in their system to ensure proper configuration. 

    Regards,
    Justin