TCAN4550: Problem with sending back ACK data, timing isue and GLOBALERR

Hi Seba,

As defined in the CAN Standards, the receiver is to send an ACK pulse immediately following the completion of a message on the bus coming from a different transmitting node.  This must be within the immediate bit periods following the message and if the receiving node does not send an ACK pulse on the bus, then the transmitting node will consider that a failed message, increase the transmit error counter, and then try to send the message again.  The receiver node will also increase its receive error counter.

In the TCAN4550, the CAN FD controller handles this ACK pulse in hardware if it has received the message error free and it is not possible for there to be a 90-100mS delay.  Perhaps we are using the ACK term to mean two different things.  Do you expect the receiving node to transmit a message back to the original transmitting node as an "Acknowledgement" that it received a message?  If so then a delay of 90-100mS could be understood and would be a result of the MCU firmware routine.

The GLOBALERR is the Logical OR of all faults in registers 0x0820 and 0x0824, therefore if it is being set then there is another fault bit being set as well.  Can you read both registers 0x0820 and 0x0824 so that we can see which fault is setting the GLOBALERR flag?

Regards,

Jonathan

Hi Jonathan

Thank you for a very quick reply.  I interpret ACK completely wrong, what I meant with this is the message which is broadcasted back to the transmitter. Sorry for misunderstanding. Like you suggested, I also think it is a firmware related issue. Do you maybe have some tips, how to lower this time? Maybe with filters?

Hi Sebastijan,

I thought that ACK message was what you meant, and it looks like your system is generally working properly.  There is probably some room for improvement on the response delay but this is unfortunately one of the few areas of the TCAN4550 that can be difficult to manage due to the SPI interface.

Since I don't have any specific details on your system requirements and architecture, I can only speak in general terms.  But here are some thoughts to consider:

1. Are you using a hardware interrupt routine, or are you polling the status and interrupt registers to determine when a new message has been received?
   
   1. If you are polling the registers, you should consider using a hardware interrupt pin so reduce the SPI bus overhead and allow an immediate response to be triggered as soon as the interrupt pin is set.
   2. If you are already using an interrupt signal, consider using one of the GPIO1 or GPO2 pins as a dedicated MCAN Message Interrupt line which will allow you separate the RX Messages from the rest of the possible interrupt flags.  This can allow your Interrupt Routine to immediately start reading the RX Message instead of spending time decoding the Interrupt register value and determine the cause of the interrupt flag which could come from numerous unrelated flags.
2. The most significant delay will come from the SPI Overhead and time required to read and write data into the TCAN4550.
   
   1. Use the fastest SPI frequency possible.  The only limitation is that it must be less than 18Mhz, or less than the crystal frequency by about 1Mhz if a clock frequency less than 20Mhz is used.  This is to ensure that the data can pass between the Digital core clock domain and SPI clock domain without error.  But reducing the SPI bit time will reduce the overall delay by a proportional amount.
   2. Use SPI Burst Reads and Writes to read and write from the RX/TX Message buffers.  If you are reading each 32bit word one at a time, half of each SPI transaction is the address and straight overhead that adds up to a significant delay.  However, if you do a Burst Read/Write, you only pass the initial start address and overhead bits on the first transaction and the rest of the transaction is only data related.
3. Is the receiving node configured to echo the message back to the sending node, or does it simply need to send an acknowledgement message without sending any specific data payload that must be generated at the time of request or after the original message has been received?
   1. If an acknowledgement message is all that is needed, you could have a specific message already stored in a specific TX Buffer and as soon as you see the interrupt flag from the received message, the MCU can immediately issue a transmit request to this specific TX Buffer and send a message back on the bus.  This is possibly the fastest way a response is possible, but the message data payload has to be preloaded in the TX Buffer. But this eliminates all of the SPI bus overhead and the time needed to read the RX Buffer or RX FIFO, process the message in the MCU, and then reload a new message in a TX Buffer and then issue a send request.
   2. If you need to pass a meaningful data payload in the response message, then use the SPI Burst Mode to fill the buffers and consider using the smallest possible data payload.
   3. Reduce as much overhead in the MCU code to allow the fastest response and processing of the received message and sending the response message.

4. This probably doesn't apply in your two board system, but in larger systems you may get delays due to the message Identifier chosen.  In CAN the messages are transmitted in a priority system with the lowest ID receiving the highest priority.  If there is a lot of traffic on the bus, you should use the lowest possible ID value to ensure it is given the appropriate priority level in the system.

I hope this gives you some ideas on how to optimize your system for a faster response.

Regards,

Jonathan

Hi Jonathan,

Thank you for your answer and tips. I will describe system a little bit:

We are using architecture as master and other nodes are slaves. Master is sending messages(asking other nodes for data) and expect acknowledgement message within 100ms. Data is send from master roughly every 8-10ms. TCAN4550 usually respond within 1m, which is more than perfect. I am using external interrupt and then reading data, same practice as you have in example. But as you can se there are some gaps between data (bottom picture). I was able to shrink amount of this gaps that i lower this parameter to 1 or 2:

"MRAMConfiguration.Rx0NumElements = 1; // RX0 Number of elements"

I was also try to setup filter but i was not successful can you help me with that?

i want to have filter to se only two messages: ID-0x6A8 and ID-0x6A9

Question about filter - if message is outside filter does it trigger interrupt?

Zoomed picture: you can see to stripes together first is request and second is answer, in the middle you can see big gap which i want to get rid off.

Regards.

Sebastijan

Hi Sebastijan,

There are a couple of different ways you could structure your filters, but here is one suggestion. I have not been able to test it out in hardware myself, but I can do so if needed. However let’s see if this is enough to get you moving in the right direction.

For additional information on the Filters there is a pretty good write up on them in the TCAN45xx Software User’s Guide.

https://www.ti.com/lit/ug/sllu270/sllu270.pdf

Section 4.2 covers the Message RAM configuration and section 4.2.3 discusses the 11-bit Standard ID filters (SID Filters) which I think is what you want.

More information on the Bosch M_CAN CAN FD Controller can be found on Bosch’s website at the following link. It was not practical to duplicate all of the information about M_CAN in the TCAN4550 datasheet especially since it is very well documented by Bosch. This User’s Guide is a great supplemental resource to the TCAN4550 Datasheet and Software User’s Guide.
https://www.bosch-semiconductors.com/ip-modules/can-ip-modules/m-can/

But generally speaking you will need to create a Standard ID Filter Element which is a 32-bit word and write that to the SID Filter Element section of your MRAM configuration. The details of a SID Filter Element are as follows:

SID Filter Element

SFT

SFEC

Final SID Filter Element

This will make your Final SID Filter Element = 0x2EA806A9

Now you will have to configure the Standard ID Filter Configuration (SIDFC) register with the number of SID Filter elements and the Start Address of the standard Message ID filter list (32-bit word address) so that M_CAN knows where to look for the start of the SID Filter List when it receives a message and how many filters are in the list. The search always starts at the first SID Filter Element in the list so if you have more than one filters, you should sequence them in a prioritized manner in MRAM to speed up the filter process. The SIDFC Register configuration details are as follows:

Standard ID Filter Configuration (address 0x1084)

LSS[7:0] List Size Standard

FLSS[15:2] Filter List Standard Start Address

If you are using a variant of the TCAN4550_DEMO code, the following structs are available to hold the settings:

TCAN4x5x_SID_SFEC_Values

TCAN4x5x_SID_SFT_Values

TCAN4x5x_MRAM_Config

TCAN4x5x_MCAN_SID_Filter

typedef enum

{

   //! Disabled filter. This filter will do nothing if it matches a packet

   TCAN4x5x_SID_SFEC_DISABLED         = 0x0,

   //! Store in RX FIFO 0 if the filter matches the incoming message

   TCAN4x5x_SID_SFEC_STORERX0         = 0x1,

   //! Store in RX FIFO 1 if the filter matches the incoming message

   TCAN4x5x_SID_SFEC_STORERX1         = 0x2,

   //! Reject the packet (do not store, do not notify MCU) if the filter matches the incoming message

   TCAN4x5x_SID_SFEC_REJECTMATCH     = 0x3,

   //! Store in default location but set a high priority message interrupt if the filter matches the incoming message

   TCAN4x5x_SID_SFEC_PRIORITY         = 0x4,

   //! Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming message

   TCAN4x5x_SID_SFEC_PRIORITYSTORERX0 = 0x5,

   //! Store in RX FIFO 1 and set a high priority message interrupt if the filter matches the incoming message

   TCAN4x5x_SID_SFEC_PRIORITYSTORERX1 = 0x6,

   //! Store in RX Buffer for debug if the filter matches the incoming message. SFT is ignored if this is selected.

   TCAN4x5x_SID_SFEC_STORERXBUFORDEBUG = 0x7

} TCAN4x5x_SID_SFEC_Values;

typedef enum

{

   //! Disabled filter. This filter will match nothing

   TCAN4x5x_SID_SFT_DISABLED           = 0x3,

   //! Classic filter with SFID1 as the ID to match, and SFID2 as the bit mask that applies to SFID1

   TCAN4x5x_SID_SFT_CLASSIC           = 0x2,

   //! Dual ID filter, where both SFID1 and SFID2 hold IDs that can match (must match exactly)

   TCAN4x5x_SID_SFT_DUALID             = 0x1,

   //! Range Filter. SFID1 holds the start address, and SFID2 holds the end address. Any address in between will match

   TCAN4x5x_SID_SFT_RANGE             = 0x0

} TCAN4x5x_SID_SFT_Values;

You should be able to simply modify the TCAN4x5x_MCAN_SID_Filter element with your new values. This is the code as written in the DEMO code in the main.c file:

       /* Setup filters, this filter will mark any message with ID 0x055 as a priority message */

       TCAN4x5x_MCAN_SID_Filter SID_ID = {0};

       SID_ID.SFT = TCAN4x5x_SID_SFT_CLASSIC;                                   // SFT: Standard filter type. Configured as a classic filter

       SID_ID.SFEC = TCAN4x5x_SID_SFEC_PRIORITYSTORERX0;                  // Standard filter element configuration, store it in RX fifo 0 as a priority message

       SID_ID.SFID1 = 0x055;                                                                 // SFID1 (Classic mode Filter)

       SID_ID.SFID2 = 0x7FF;                                                                 // SFID2 (Classic mode Mask)

       TCAN4x5x_MCAN_WriteSIDFilter(0, &SID_ID);                                // Write to the MRAM

You should be able to modify it as follows for your desired settings:

       /* Setup filters, this filter will mark any message with ID 0x6A8 or 0x6A9 as a priority message */

       TCAN4x5x_MCAN_SID_Filter SID_ID = {0};

       SID_ID.SFT = TCAN4x5x_SID_SFT_RANGE;                                     // SFT: Range Filter type. Configured as a range filter

       SID_ID.SFEC = TCAN4x5x_SID_SFEC_PRIORITYSTORERX0;                  // Standard filter element configuration, store it in RX fifo 0 as a priority message

       SID_ID.SFID1 = 0xA68;                                                                 // SFID1 (Range Filter Start ID)

       SID_ID.SFID2 = 0xA69;                                                                 // SFID2 (Range Filter End ID)

       TCAN4x5x_MCAN_WriteSIDFilter(0, &SID_ID);                                // Write to the MRAM

The code will configure the SID Filter Elements as part of the following function:

TCAN4x5x_MRAM_Configure(TCAN4x5x_MRAM_Config *MRAMConfig)

I hope this is clear and helpful. If you still have questions, please let me know.

Regards,

Jonathan

Hi Jonathan,

Thank you for detailed explanation.

I tried your suggestion and i think i checked everything three times but its not working as expected.

My settings for filters are:

/* Configure the default CAN packet filtering settings */
TCAN4x5x_MCAN_Global_Filter_Configuration gfc = {0};
gfc.RRFE = 1; // Reject remote frames (TCAN4x5x doesn't support this)
gfc.RRFS = 1; // Reject remote frames (TCAN4x5x doesn't support this)
gfc.ANFE = TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0; // Default behavior if incoming message doesn't match a filter is to accept into RXFIO0 for extended ID messages (29 bit IDs)
gfc.ANFS = TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0; // Default behavior if incoming message doesn't match a filter is to accept into RXFIO0 for standard ID messages (11 bit IDs)

TCAN4x5x_MCAN_SID_Filter SID_ID = {0};
SID_ID.SFT = TCAN4x5x_SID_SFT_RANGE; // SFT: Standard filter type. Configured as a classic filter
SID_ID.SFEC = TCAN4x5x_SID_SFEC_PRIORITYSTORERX0; // Standard filter element configuration, store it in RX fifo 0 as a priority message
SID_ID.SFID1 = 0x6A8; // SFID1 (Classic mode Filter)
SID_ID.SFID2 = 0x6A9; // SFID2 (Classic mode Mask)
TCAN4x5x_MCAN_WriteSIDFilter(0, &SID_ID); // Write to the MRAM

TCAN4x5x_MCAN_EnableProtectedRegisters(); // Start by making protected registers accessible
TCAN4x5x_MCAN_ConfigureCCCRRegister(&cccrConfig); // Enable FD mode and Bit rate switching
TCAN4x5x_MCAN_ConfigureGlobalFilter(&gfc); // Configure the global filter configuration (Default CAN message behavior)
TCAN4x5x_MCAN_ConfigureNominalTiming_Simple(&TCANNomTiming); // Setup nominal/arbitration bit timing
TCAN4x5x_MCAN_ConfigureDataTiming_Simple(&TCANDataTiming); // Setup CAN FD timing
TCAN4x5x_MRAM_Clear(); // Clear all of MRAM (Writes 0's to all of it)
TCAN4x5x_MRAM_Configure(&MRAMConfiguration); // Set up the applicable registers related to MRAM configuration
TCAN4x5x_MCAN_DisableProtectedRegisters(); // Disable protected write and take device out of INIT mode

At firs i thought that i did not set something right, but then i went to debugger and start observing registers.

i was looking for that SID Element that you suggested:

This will make your Final SID Filter Element = 0x2EA806A9

Here is picture from debuger.

As you can see everything is correct.

But when i start to observe system and messages, the system jumps to interrupt rutine when unwanted message comes, look the picture.

RXMsgHeader.ID == PDR (PDR = 0x6A8) 

RXMsgHeader.ID == 0x560 (unwanted message)

I don't know exactly what am i doing wrong, do you have a clue maybe? 

Regards.

Sebastijan

Hi Sebastijan,

I think the ANFS[1:0] and ANFE[1:0] bit fields may be set wrong in the Global Filter Configuration address 0x1080.  By default they are set to 2'b00 which means they will accept any message frame that does not match a filter and place them into RX FIFO 0.  If you accept a filtered message and store it into RX FIFO 0 while accepting all non-matching frames and storing them into RX FIFO 0, you are still going to receive every message and get an interrupt for each one.

You can change these bit fields to either 2'b10 or 2'b11 which will reject any message frame that does not match a filter.  Or you can set it up such that filtered messages go into one storage location such as RX FIFO 0 or a RX Buffer which could be thought of as high priority messages, and any non-matching messages could be directed to a different location such as RX FIFO 1. 

Try checking the GFC register and make sure that ANFS and ANFE are set to "Reject" non-matching messages and try your test again. 

Regards,

Jonathan

Hi Jonathan,

Thank you very very much for answer. It helped a lot, but i have to add little change.

I set registers as you advise:

gfc.ANFE = TCAN4x5x_GFC_REJECT;
gfc.ANFS = TCAN4x5x_GFC_REJECT;

But problem was also in this settings:

MRAMConfiguration.SIDNumElements = 2;
MRAMConfiguration.XIDNumElements = 0;

I had to change this XIDNumElements from zero to 1, if it is set to zero filtering is not working.

MRAMConfiguration.SIDNumElements = 2;
MRAMConfiguration.XIDNumElements = 1;

Here is the result its amazing how quick it is.

As you can see on picture there is no gaps, like before. Now i can even increase FIFO to 5 elements and it does not effect speed.

Now i have got last question.

The system will grow with development and of course new things will be send over can. Now can accept only two messages and filter is set that it is allowing  messages between SFID1 and SFID2. If i want to set filter with 5 or 10 elements with totally different IDs, how can i set this properly?

Sorry for a lot of questions but product will go to mass production next year and it have to work properly:)

Regards

Seba

Hi Jonathan,

Thank you for all the help!

Regards.

Seba