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DP83867CS: DP83867CSRGZT-- Getting Error frames

AKASH JAIN
Intellectual 620 points
Part Number: DP83867CS

Hello 

We are using DP83867CSRGZT in one of our designs and we are getting the same issue.

We are using the PHY in RGMII mode, and 10/100 Speed only.

The PHY is connected to FPGA and we are using External Ethernet Analyzer to send and receive data, but we are getting FCS errors) in the Analyser. ( (we tried shifted RX and TX clock in all possible ways)

Also, we tried to check the issue using the DP83867 Troubleshooting Guide and the below points are checked and found OK.

1. Power supplies are fine

2. RBIAS Voltage and resistance is fine

3. Reset and clock are also fine

4. We are able to read and write on MDIO.

5. Reverse loopback is working fine but MII loopback is not working fine(We are not getting correct data in FPGA)

 

PFA Schematic for your reference, Can you please verify once and let us know how this can be resolved.


 

Regards

Akash

  • 0
    TI__Expert 7040 points

    Hi Akash,

    Can you provide details on how you are performing MII loopback? Can you also share if Digital and Analog loopback modes are showing errors?

    The only strap resistor set to a non-default value is the RX_CTRL strap correct? I don't see any issues with the schematic. Can you share how long the connections are between the PHY and RJ45 as well as RGMII traces? Layout or noise could be an issue with the PHY functionally working but seeing errors.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 620 points

    Hello Justin 

    Please see the information below:

    From FPGA We are sending the incremental data(from 0 to 256)  continuously on TX lines.

     1. Writing register 0x001F to 0x8000 to apply a software reset.
     2. Writing register 0x0000 to 0x0100 to force 10BASE-T operation.
    3. Write register 0x0032 to 0x00D3 to enable RGMII.
    4.   Writing register 0x0000 to 0x4100 to enable MII loopback in 10Mbps mode
    5. Write register 0x001F to 0x4000 to apply a software restart.

    Same for 100Mbps mode but the only thing is we write 0x6100 in 0x0 register of PHY,

    Regarding Traces in the layout please see the details below:

    1. From Phy to RJ45: 500mils

    2. RGMII signals: RX signal range from 2300 mils to 2500mils and the TX signal range from 2100 mils to 2300 mils.

    Regards

    Akash

  • 0 in reply to AKASH JAIN
    TI__Expert 7040 points

    Hi Akash, 

    Are you seeing the CRC errors in both 10M and 100M modes? Please provide the crystal oscillator part number and verify it meets the PHY design requirements. Can you also confirm that the RBIAS resistor is 1% tolerance?

    Can you verify that you are seeing CRC errors in digital and analog loopback as well as MII loopback? You can set register 0x0016 = 0x0004 (digital loopback) or 0x0008 (analog loopback), without setting MII loopback bits. 

    Another test I'd like to verify is if the 33ohm series resistor are removed from the TX and RX paths, do you still see errors?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 620 points

    Hello Justin

    Yes, we are seeing the CRC errors in both 10M and 100M modes.

    Crystal Oscillator part no: ABM8G-25.000MHZ-18-D2Y-T

    RBIAS Resistor part no: RC0603FR-0711KL, 1% tolerance.

    We tried digital and analog loopback but it did not return any data to FPGA.

    We are testing by replacing 33 ohms with 0ohm as a series resistor and will update the same.

    Regards

    Akash Jain

  • 0 in reply to AKASH JAIN
    TI__Expert 7040 points

    Hi Akash,

    The load capacitance for the crystal you provided is 18pF. However, you have two 18pF caps on either side of the crystal giving you a greater load capacitance on XTAL than specified. I would recommend populating 9pF - 12pF caps to meet the XTAL load capacitance in the datasheet.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 620 points

    Hello Justin

    We checked by replacing 33 ohms with 0 ohms and also checked by changing the load capacitance to 10pF but still we are facing the same issue.

    Can you suggest what we can do now?

    Regards

    Akash

  • 0 in reply to AKASH JAIN
    TI__Expert 7040 points

    Hi Akash,

    Can you share the register configuration you are using for digital and analog loopback? I expect those modes to be functional in your setup, no data returned could be a related issue. 

    Can you also verify that there are no pins on the FPGA with internal pull-up/pull-down configurations connected to the DP83867 strap pins? This could put the device into a strap setting you are not expecting. 

    What is the frequency of the CRC errors you are seeing? Is it the same in normal operation as MII loopback mode?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 620 points

    Hello Justin

    We are able to make the interface up, actually, there was swapping in TXD2 and TXD1 in the schematic that was causing the issue.

    Thanks, Justin for all the help and support.

    Regards

    Akash Jain