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DP83867IS: DP83867ISRGZ interrupt status register

Obinna Ezeilo
Intellectual 2385 points
Part Number: DP83867IS

Hi team, 

A customer who's been using DP83867IS sent the below note regarding an issue they've been facing for a while. 

Currently for production testing we are testing the Ethernet connection between a PC, TI DP83867ISRGZ and processor. We are using the Interrupt Status register (0x0013) to determine if there are status changes during the test. The register one time to clear it (clear on read) and then continuously monitor if the register doesn't change status. The DUT remains connected with the Ethernet cable and link status is validated before the test by reading register 0x1 with the MII interface. This test mechanism worked fine for about 100 to 200 units. Now we see some DUT's on which the status changes after a random amount of reads. There are three bits which change state (sometimes one bit, sometimes all three bits):

  • Bit 10: Link status changed: Assumed to indicate if the PHY successfully reads link pulses and is toggled when the cable is pulled. Is this register reliable or can this error register give false calls?
  • Bit 8: False carrier interrupt: Is there more information available what this bit indicates? This is not specified in the datasheet.
  • Bit 2: xGMII Error interrupt: Does this bit indicates an hardware failure between the SGMII and processor, or is this a software/protocol driven bit indicating errors? More information under which conditions this bit toggles would be appreciated.

Could you please give more information if reading the Interrupt status register is a reliable way to test interface changes and give answers to questions above?

Thanks for the support. 

BR, 

Obinna. 

  • 0
    TI__Expert 7040 points

    Hi Obinna,

    Link Status Change interrupt is reliable in determining if the PHY has lost or regained link. Are you able to confirm if a link change has occurred when the interrupt indicates?

    False Carriers are defined as carrier event packets not beginning with /S/. /S/ denotes the Start_of_Packet delimiter; /S/ = /K27.7/ and is used to delineate the starting boundary of a data sequence. To clear this interrupt, read the MISR1 register and to reset the False Carrier sense counter, read the FCSCR register.

    The xGMII Error interrupt indicates that the MAC interface has encountered an error. It does not count errors in data being transferred as interrupts. 

    Regards,
    Justin