DS110DF410EVM: Register 0xFF set to 0xA5 every time I set bit [2] high.

Leonardo Marcon

Part Number: DS110DF410EVM

Hello everyone,

I am using the re-timer board DS110DF410EVM to generate high-frequency PRBS signals (10Gbps) on all four output channels.

Unfortunately, when I try to set up register 0xFF for writing on the channels register sets (setting bit [2] of 0xFF high, according to the datasheet), the value of the register 0xFF immediately change to 0xA5 and I lose the possibility of changing the value of any other bit. If I set bit [2] to low, the other bits becomes accessible once again. I am pretty sure that the I2C interface is working properly because I can easily read and write the other registers and the results is the expected one.

The procedure I am following is:

- I power up the board (3.3V, current limit at 1500mA to avoid issues with current spikes at start-up, even if the board does not seems to requires more than 400mA)

- I check the connection of the through the I2C

- I read the register 0xFF and check that its value is indeed 0x00 (as it should be by default)

- I write the value 0x04 in register 0xFF to allow read/write operations on ch0 register set.

- I read register 0xFF again and observe that instead of 0x04 the register read 0xA5

The interesting part is that while register 0xFF is in this state, which according to the datasheet should allow the write/read operation of ch1 register set, the register set of ch0 is instead accessible for write/read. I made some tests and indeed while register 0xFF has the value 0xA5, I can generate the PRBS signal on ch0, set its output voltage and the de-emphasis (thus confirming once again that the I2C interface should be working fine).

Unfortunately I do not have the USBtoI2C tool to test the board with its GUI, but I still hope that what I am missing is just a small detail in my procedure.

Thanks for your help,

Leo

over 4 years ago

0 Rodrigo Natal over 4 years ago

TI__Mastermind 19235 points

Hi,

What happens when you select other channels? If 0xFF = 0x00 and you then perform write to select channel 2, do you also then observe 0xA5 when you read 0xFF?

Table. Channel Select Register Values Mapped to Register Set Target

REGISTER 0xff VALUE (hex)	SHARED/CHAN NEL REGISTER SELECTION	BROADCAST CHANNEL REGISTER SELECTION	TARGETED CHANNEL SELECTIO N	COMMENTS
0x00	Shared	N/A	N/A	All reads and writes target shared register set
0x04	Channel	No	0	All reads and writes target channel 0 register set
0x05	Channel	No	1	All reads and writes target channel 1 register set
0x06	Channel	No	2	All reads and writes target channel 2 register set
0x07	Channel	No	3	All reads and writes target channel 3 register set
0x0c	Channel	Yes	0	All writes target all channel register sets, all reads target channel 0 register set
0x0d	Channel	Yes	1	All writes target all channel register sets, all reads target channel 1 register set
0x0e	Channel	Yes	2	All writes target all channel register sets, all reads target channel 2 register set
0x0f	Channel	Yes	3	All writes target all channel register sets, all reads target channel 3 register set

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 Leonardo Marcon over 4 years ago in reply to Rodrigo Natal

Prodigy 30 points

Dear Rodrigo,

I observe 0xA5 every time I write a value that set the bit [2] of 0xFF to high, thus I read 0xA5 for all the values in the table.

Best,

Leo

0 Rodrigo Natal over 4 years ago in reply to Leonardo Marcon

TI__Mastermind 19235 points

Hi,

There might be an issue with the read values for this 0xFF register. I would suggest to not pay mind to it if your desired channel selection configuration is actually taking effect.