DS110DF111: SPF + AOC can't established

Robin Liu

Intellectual 1930 points

Part Number: DS110DF111

hi Team,

there is a issue from my customer for the DS110DF111 design, could you please help how to deal with it? Thanks.

we have been able to enable SFP+ DAC, but SFP+ AOC still does not work.

Could you help us clarify the issue that cannot be established physical link in SPF + AOC?

Currently, our configuration of the control pins is as follows:
RX_LOS : SFP+ Pin8 => GPIO3_DAT04 (IN / Low)
MOD-ABS : SFP+ Pin6 => GPIO3_DAT06 (IN / Low)
LOS/INT : Retimer Pin13 => GPIO3_DAT00 (IN / Low)
TX_Disable : SFP+ Pin3 => GPIO3_DAT04 (OUT / Low)
TXFAULT : SFP+ Pin2 => GPIO3_DAT04 (IN / Low)

regards,

Robin Liu

over 4 years ago

0 Rodrigo Natal over 4 years ago

TI__Mastermind 19235 points

Hi,

Can you provide a DS110DF111 retimer registers dump when for when issue is observed? I'm in particular interested in the values of channel registers 0x02, 0x03, 0x27, 0x28, and 0x52.

Thanks,

Rodrigo Natal

HSSC Applications Engineer

0 Robin Liu over 4 years ago in reply to Rodrigo Natal

TI__Intellectual 1930 points

Fullscreen T99B225_Retimer_RegisterDump_uBootLog.txt Download

NOTICE:  BL2: v1.5(release):
NOTICE:  BL2: Built : 01:03:50, Sep 29 2020
NOTICE:  UDIMM 18ASF4G72HZ-2G6B1 
NOTICE:  DDR4 UDIMM with 2-rank 64-bit bus (x8)

NOTICE:  64 GB DDR4, 64-bit, CL=17, ECC on, 256B, CS0+CS1
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v1.5(release):
NOTICE:  BL31: Built : 01:03:55, Sep 29 2020
NOTICE:  Welcome to LX2160 BL31 Phase


U-Boot 2019.10 (Sep 29 2020 - 01:03:34 +0000)

SoC:  LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
       CPU0(A72):2000 MHz  CPU1(A72):2000 MHz  CPU2(A72):2000 MHz  
       CPU3(A72):2000 MHz  CPU4(A72):2000 MHz  CPU5(A72):2000 MHz  
       CPU6(A72):2000 MHz  CPU7(A72):2000 MHz  CPU8(A72):2000 MHz  
       CPU9(A72):2000 MHz  CPU10(A72):2000 MHz  CPU11(A72):2000 MHz  
       CPU12(A72):2000 MHz  CPU13(A72):2000 MHz  CPU14(A72):2000 MHz  
       CPU15(A72):2000 MHz  
       Bus:      700  MHz  DDR:      2400 MT/s
Reset Configuration Word (RCW):
       00000000: 50636338 20500050 00000000 00000000
       00000010: 00000000 0c010000 00000000 00000000
       00000020: 016001a0 00002580 00000000 00000096
       00000030: 09240000 00000001 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 00027000 00000000
       00000070: 00a70030 00150020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev2.0-RDB, Board version: O, boot from SD
FPGA: v255.255
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
VID: failed to select VDD Page 0
VID: Couldn't read sensor abort VID adjustment
core voltage not adjusted
DRAM:  63.9 GiB
DDR    63.9 GiB (DDR4, 64-bit, CL=17, ECC on)
       DDR Controller Interleaving Mode: 256B
       DDR Chip-Select Interleaving Mode: CS0+CS1
Using SERDES1 Protocol: 7 (0x7)
Using SERDES2 Protocol: 5 (0x5)
Using SERDES3 Protocol: 0 (0x0)
SERDES3[PRTCL] = 0x0 is not valid
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

EEPROM: Invalid ID (ff ff ff ff)
In:    serial_pl01x
Out:   serial_pl01x
Err:   serial_pl01x
Net:   DPMAC5@xgmii running firmware version 5.4.B
DPMAC5@xgmii: system interface XFI
DPMAC5@xgmii: Aquantia AQR113 Firmware Version 5.4.b
PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 disabled
PCIe2: pcie@3600000 Root Complex: no link
PCIe3: pcie@3700000 disabled
PCIe4: pcie@3800000 disabled
PCIe5: pcie@3900000 disabled
DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth0) using random MAC address - b2:63:9a:1c:0b:45
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth1) using random MAC address - 0a:fd:0c:1b:b5:84
, DPMAC5@xgmii
Warning: DPMAC5@xgmii (eth2) using random MAC address - 16:c4:5f:1c:db:99
, DPMAC6@xgmii
Warning: DPMAC6@xgmii (eth3) using random MAC address - ba:01:56:dd:c5:91
, DPMAC7@sgmii
Warning: DPMAC7@sgmii (eth4) using random MAC address - 06:84:c2:92:0a:8a
, DPMAC8@sgmii
Warning: DPMAC8@sgmii (eth5) using random MAC address - 32:a1:dd:1d:9b:e5
, DPMAC9@sgmii
Warning: DPMAC9@sgmii (eth6) using random MAC address - fe:7f:3d:ea:7f:2c
, DPMAC10@sgmii
Warning: DPMAC10@sgmii (eth7) using random MAC address - e2:75:e1:bd:76:a4
, DPMAC17@rgmii-id
Warning: DPMAC17@rgmii-id (eth8) using random MAC address - fe:36:3b:16:3c:84
, DPMAC18@rgmii-id
Warning: DPMAC18@rgmii-id (eth9) using random MAC address - 1e:23:44:b1:18:68


MMC read: dev # 0, block # 20480, count 4608 ... 4608 blocks read: OK

MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK
crc32+ 
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.20.4, boot status: 0x1)
Hit any key to stop autoboot:  0 
=> setenv ipaddr 192.168.0.100
=> saveenv
Saving Environment to MMC... Writing to MMC(0)... OK
=> ping 192.168.0.1
Using DPMAC3@xgmii device
host 192.168.0.1 is alive
=> i2c dev 0
Setting bus to 0
=> i2c mw 0x77 0x00 0x0e
=> i2c md 0x18 0x00 0x100
0000: 00 00 dc 00 00 00 00 00 00 24 10 0f 08 00 93 69    .........$.....i
0010: 3a 20 a0 90 00 10 7a 25 00 23 00 03 24 00 21 55    : ....z%.#..$.!U
0020: 00 00 00 40 00 00 00 25 64 20 30 00 72 83 00 06    ...@...%d 0.r...
0030: 00 40 11 88 bf 1f 33 02 10 00 a5 33 8e 00 80 00    .@....3....3....
0040: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
0050: 00 00 80 00 80 00 00 00 b0 95 e9 d5 99 a5 e6 f9    ................
0060: 00 b2 90 b3 cd 00 00 00 00 0a 44 40 00 00 00 00    ..........D@....
0070: 03 20 00 00 00 00 00 00 b0 95 e9 d5 99 a5 e6 f9    . ..............
0080: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
0090: 00 00 80 00 80 00 00 00 b0 95 e9 d5 99 a5 e6 f9    ................
00a0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00b0: 00 00 80 00 80 00 00 00 b0 95 e9 d5 99 a5 e6 f9    ................
00c0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00d0: 00 00 80 00 80 00 00 00 b0 95 e9 d5 99 a5 e6 f9    ................
00e0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00f0: 00 00 80 00 80 00 00 00 b0 95 e9 d5 99 a5 e6 0c    ................
=> i2c mw 0x18 0xff 0x0
=> i2c md 0x18 0x00 0x100
0000: 00 60 00 00 01 00 00 04 00 00 00 00 00 00 00 00    .`..............
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
=> i2c md 0x50 0x00 0x100
0000: 03 04 21 00 00 00 00 00 04 00 00 00 67 00 00 00    ..!.........g...
0010: 00 00 01 00 43 49 53 43 4f 2d 4d 4f 4c 45 58 20    ....CISCO-MOLEX 
0020: 20 20 20 20 00 00 09 3a 37 34 37 35 32 2d 39 30        ...:74752-90
0030: 34 34 20 20 20 20 20 20 30 37 20 20 01 00 00 09    44      07  ....
0040: 00 00 00 00 4d 4f 43 31 34 31 38 30 30 34 34 20    ....MOC14180044 
0050: 20 20 20 20 31 34 30 35 30 33 20 20 00 00 00 82        140503  ....
0060: 80 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 0b 42 33 25    .............B3%
0080: 43 4f 50 51 41 41 34 4a 41 41 33 37 2d 30 39 36    COPQAA4JAA37-096
0090: 30 2d 30 32 56 30 32 20 01 00 46 00 00 00 00 c9    0-02V02 ..F.....
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 53 46 50 2d 48 31 30 47 42 2d 43 55 31 4d 20 20    SFP-H10GB-CU1M  
00d0: 20 20 20 20 30 37 00 00 00 00 00 00 00 00 00 b2        07..........
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

hi Rodrigo,

Attached, please let me know if you have more question, Thanks

regards,

Robin Liu

0 Rodrigo Natal over 4 years ago in reply to Robin Liu

TI__Mastermind 19235 points

Hi,

The retimer status registers seem to show healthy values.

0x02 = 0xDC-> CDR is locked and happy
0x27, 0x28 ->These registers contain the retimer eye opening values. The values being observed here meet and exceed our recommended minimum criteria. HEO = 0.57UI and VEO = 312.5mV
0x52 = 0x80 -> This is the current CTLE boost setting. I would deem this CTLE setting as adequate given the reasonable eye opening values being observed

At this point I don't think the retimer is the problem.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 Robin Liu over 4 years ago in reply to Rodrigo Natal

TI__Intellectual 1930 points

Fullscreen T99B225_Retimer_AOC_RegisterDump_uBootLog.txt Download

NOTICE:  BL2: v1.5(release):
NOTICE:  BL2: Built : 07:31:11, Oct  5 2020
NOTICE:  UDIMM 18ASF4G72HZ-2G6B1 
NOTICE:  DDR4 UDIMM with 2-rank 64-bit bus (x8)

NOTICE:  64 GB DDR4, 64-bit, CL=17, ECC on, 256B, CS0+CS1
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v1.5(release):
NOTICE:  BL31: Built : 07:31:15, Oct  5 2020
NOTICE:  Welcome to LX2160 BL31 Phase


U-Boot 2019.10 (Oct 05 2020 - 07:30:55 +0000)

SoC:  LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
       CPU0(A72):2000 MHz  CPU1(A72):2000 MHz  CPU2(A72):2000 MHz  
       CPU3(A72):2000 MHz  CPU4(A72):2000 MHz  CPU5(A72):2000 MHz  
       CPU6(A72):2000 MHz  CPU7(A72):2000 MHz  CPU8(A72):2000 MHz  
       CPU9(A72):2000 MHz  CPU10(A72):2000 MHz  CPU11(A72):2000 MHz  
       CPU12(A72):2000 MHz  CPU13(A72):2000 MHz  CPU14(A72):2000 MHz  
       CPU15(A72):2000 MHz  
       Bus:      700  MHz  DDR:      2400 MT/s
Reset Configuration Word (RCW):
       00000000: 50636338 20500050 00000000 00000000
       00000010: 00000000 0c010000 00000000 00000000
       00000020: 016001a0 00002580 00000000 00000096
       00000030: 09240000 00000001 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 00027000 00000000
       00000070: 00a70030 00150020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev2.0-RDB, Board version: O, boot from SD
FPGA: v255.255
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
VID: failed to select VDD Page 0
VID: Couldn't read sensor abort VID adjustment
core voltage not adjusted
DRAM:  63.9 GiB
DDR    63.9 GiB (DDR4, 64-bit, CL=17, ECC on)
       DDR Controller Interleaving Mode: 256B
       DDR Chip-Select Interleaving Mode: CS0+CS1
board_retimer_init: Cannot find udev for a bus 0
Using SERDES1 Protocol: 7 (0x7)
Using SERDES2 Protocol: 5 (0x5)
Using SERDES3 Protocol: 0 (0x0)
SERDES3[PRTCL] = 0x0 is not valid
MMC:   FSL_SDHC: 0
Loading Environment from MMC... OK
EEPROM: Read failed.
In:    serial_pl01x
Out:   serial_pl01x
Err:   serial_pl01x
Net:   DPMAC5@xgmii running firmware version 5.4.B
DPMAC5@xgmii: system interface XFI
DPMAC5@xgmii: Aquantia AQR113 Firmware Version 5.4.b
PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 disabled
PCIe2: pcie@3600000 Root Complex: no link
PCIe3: pcie@3700000 disabled
PCIe4: pcie@3800000 disabled
PCIe5: pcie@3900000 disabled
DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth0) using random MAC address - 92:28:6c:8c:b6:5b
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth1) using random MAC address - 82:12:97:ec:3e:3b
, DPMAC5@xgmii
Warning: DPMAC5@xgmii (eth2) using random MAC address - 3e:9d:30:b4:2f:99
, DPMAC6@xgmii
Warning: DPMAC6@xgmii (eth3) using random MAC address - 96:d4:04:50:69:e3
, DPMAC7@sgmii
Warning: DPMAC7@sgmii (eth4) using random MAC address - a2:df:98:e2:f4:cb
, DPMAC8@sgmii
Warning: DPMAC8@sgmii (eth5) using random MAC address - 96:ee:2f:81:12:9c
, DPMAC9@sgmii
Warning: DPMAC9@sgmii (eth6) using random MAC address - da:e9:46:ec:a3:60
, DPMAC10@sgmii
Warning: DPMAC10@sgmii (eth7) using random MAC address - e2:75:46:72:c2:f2
, DPMAC17@rgmii-id
Warning: DPMAC17@rgmii-id (eth8) using random MAC address - fe:34:1c:d3:08:d1
, DPMAC18@rgmii-id
Warning: DPMAC18@rgmii-id (eth9) using random MAC address - 62:ab:89:ea:0c:6e


MMC read: dev # 0, block # 20480, count 4608 ... 4608 blocks read: OK

MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK
crc32+ 
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.20.4, boot status: 0x1)
Hit any key to stop autoboot:  0 
=> 
=> setenv ipaddr 192.168.0.100
=> saveenv
Saving Environment to MMC... Writing to MMC(0)... OK
=> 
=> ping 192.168.0.1
Using DPMAC3@xgmii device

ARP Retry count exceeded; starting again
ping failed; host 192.168.0.1 is not alive
=> i2c dev 0
Setting bus to 0
=> i2c mw 0x77 0x00 0x0e
=> i2c md 0x18 0x00 0x100
0000: 00 60 00 00 01 00 00 04 00 00 00 00 00 00 00 00    .`..............
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
=> i2c mw 0x18 0xff 0xc
=> i2c md 0x18 0x00 0x100
0000: 00 00 dc 00 00 00 00 00 00 00 10 0f 08 00 93 69    ...............i
0010: 3a 20 a0 90 00 10 7a 25 40 23 00 03 24 00 e1 55    : ....z%@#..$..U
0020: 00 00 00 40 00 00 00 2e 5e 20 30 00 72 80 00 06    ...@....^ 0.r...
0030: 00 40 11 88 bf 1f 33 00 10 00 a5 33 8d 00 80 00    .@....3....3....
0040: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
0050: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
0060: 00 00 00 00 00 00 00 00 00 0a 44 40 00 00 00 00    ..........D@....
0070: 03 23 13 01 10 10 00 00 b0 95 69 d5 99 a5 e6 f9    .#........i.....
0080: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
0090: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
00a0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00b0: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
00c0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00d0: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
00e0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00f0: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 0c    ..........i.....
=> i2c md 0x50 0x00 0x100
0000: 03 04 07 20 00 00 00 00 00 00 00 03 64 00 0a 64    ... ........d..d
0010: 00 00 00 00 57 54 44 20 20 20 20 20 20 20 20 20    ....WTD         
0020: 20 20 20 20 00 00 1c ad 52 54 58 4d 32 32 38 2d        ....RTXM228-
0030: 34 30 32 20 20 20 20 20 31 2e 30 20 05 1e 00 77    402     1.0 ...w
0040: 00 1a 00 00 46 52 31 38 30 31 32 38 36 38 34 20    ....FR180128684 
0050: 20 20 20 20 31 38 30 31 30 39 20 20 68 f6 03 fc        180109  h...
0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
0070: ff ff ff ff ff ff ff ff ff ff ff 80 91 a2 b3 ff    ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
=>

hi Rodrigo,

thanks for the analysis, the currently customer test result is as below;

The current test results are as follows:
# SFP+ Active Optical Cable (AOC): FAIL
# SFP+ Direct Attach Cable (DAC): PASS (previous test result)

I double checked with customer, the last time I send is the SFP +DAC, so it is no problem.

and this time, is the SFP + AOC, it fail. so please help re-check. Thanks.

regards,

Robin Liu

0 Rodrigo Natal over 4 years ago in reply to Robin Liu

TI__Mastermind 19235 points

Hi Robin,

Please then provide the retimer registers dump for the SFP+ AOC case.

Thanks,

Rodrigo

0 Robin Liu over 4 years ago in reply to Rodrigo Natal

TI__Intellectual 1930 points

hi Rodrigo,

I just attached it on the thread, and re-attached it as below. if you can see that?

Fullscreen 5751.T99B225_Retimer_AOC_RegisterDump_uBootLog.txt Download

NOTICE:  BL2: v1.5(release):
NOTICE:  BL2: Built : 07:31:11, Oct  5 2020
NOTICE:  UDIMM 18ASF4G72HZ-2G6B1 
NOTICE:  DDR4 UDIMM with 2-rank 64-bit bus (x8)

NOTICE:  64 GB DDR4, 64-bit, CL=17, ECC on, 256B, CS0+CS1
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v1.5(release):
NOTICE:  BL31: Built : 07:31:15, Oct  5 2020
NOTICE:  Welcome to LX2160 BL31 Phase


U-Boot 2019.10 (Oct 05 2020 - 07:30:55 +0000)

SoC:  LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
       CPU0(A72):2000 MHz  CPU1(A72):2000 MHz  CPU2(A72):2000 MHz  
       CPU3(A72):2000 MHz  CPU4(A72):2000 MHz  CPU5(A72):2000 MHz  
       CPU6(A72):2000 MHz  CPU7(A72):2000 MHz  CPU8(A72):2000 MHz  
       CPU9(A72):2000 MHz  CPU10(A72):2000 MHz  CPU11(A72):2000 MHz  
       CPU12(A72):2000 MHz  CPU13(A72):2000 MHz  CPU14(A72):2000 MHz  
       CPU15(A72):2000 MHz  
       Bus:      700  MHz  DDR:      2400 MT/s
Reset Configuration Word (RCW):
       00000000: 50636338 20500050 00000000 00000000
       00000010: 00000000 0c010000 00000000 00000000
       00000020: 016001a0 00002580 00000000 00000096
       00000030: 09240000 00000001 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 00027000 00000000
       00000070: 00a70030 00150020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev2.0-RDB, Board version: O, boot from SD
FPGA: v255.255
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
VID: failed to select VDD Page 0
VID: Couldn't read sensor abort VID adjustment
core voltage not adjusted
DRAM:  63.9 GiB
DDR    63.9 GiB (DDR4, 64-bit, CL=17, ECC on)
       DDR Controller Interleaving Mode: 256B
       DDR Chip-Select Interleaving Mode: CS0+CS1
board_retimer_init: Cannot find udev for a bus 0
Using SERDES1 Protocol: 7 (0x7)
Using SERDES2 Protocol: 5 (0x5)
Using SERDES3 Protocol: 0 (0x0)
SERDES3[PRTCL] = 0x0 is not valid
MMC:   FSL_SDHC: 0
Loading Environment from MMC... OK
EEPROM: Read failed.
In:    serial_pl01x
Out:   serial_pl01x
Err:   serial_pl01x
Net:   DPMAC5@xgmii running firmware version 5.4.B
DPMAC5@xgmii: system interface XFI
DPMAC5@xgmii: Aquantia AQR113 Firmware Version 5.4.b
PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 disabled
PCIe2: pcie@3600000 Root Complex: no link
PCIe3: pcie@3700000 disabled
PCIe4: pcie@3800000 disabled
PCIe5: pcie@3900000 disabled
DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth0) using random MAC address - 92:28:6c:8c:b6:5b
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth1) using random MAC address - 82:12:97:ec:3e:3b
, DPMAC5@xgmii
Warning: DPMAC5@xgmii (eth2) using random MAC address - 3e:9d:30:b4:2f:99
, DPMAC6@xgmii
Warning: DPMAC6@xgmii (eth3) using random MAC address - 96:d4:04:50:69:e3
, DPMAC7@sgmii
Warning: DPMAC7@sgmii (eth4) using random MAC address - a2:df:98:e2:f4:cb
, DPMAC8@sgmii
Warning: DPMAC8@sgmii (eth5) using random MAC address - 96:ee:2f:81:12:9c
, DPMAC9@sgmii
Warning: DPMAC9@sgmii (eth6) using random MAC address - da:e9:46:ec:a3:60
, DPMAC10@sgmii
Warning: DPMAC10@sgmii (eth7) using random MAC address - e2:75:46:72:c2:f2
, DPMAC17@rgmii-id
Warning: DPMAC17@rgmii-id (eth8) using random MAC address - fe:34:1c:d3:08:d1
, DPMAC18@rgmii-id
Warning: DPMAC18@rgmii-id (eth9) using random MAC address - 62:ab:89:ea:0c:6e


MMC read: dev # 0, block # 20480, count 4608 ... 4608 blocks read: OK

MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK
crc32+ 
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.20.4, boot status: 0x1)
Hit any key to stop autoboot:  0 
=> 
=> setenv ipaddr 192.168.0.100
=> saveenv
Saving Environment to MMC... Writing to MMC(0)... OK
=> 
=> ping 192.168.0.1
Using DPMAC3@xgmii device

ARP Retry count exceeded; starting again
ping failed; host 192.168.0.1 is not alive
=> i2c dev 0
Setting bus to 0
=> i2c mw 0x77 0x00 0x0e
=> i2c md 0x18 0x00 0x100
0000: 00 60 00 00 01 00 00 04 00 00 00 00 00 00 00 00    .`..............
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
=> i2c mw 0x18 0xff 0xc
=> i2c md 0x18 0x00 0x100
0000: 00 00 dc 00 00 00 00 00 00 00 10 0f 08 00 93 69    ...............i
0010: 3a 20 a0 90 00 10 7a 25 40 23 00 03 24 00 e1 55    : ....z%@#..$..U
0020: 00 00 00 40 00 00 00 2e 5e 20 30 00 72 80 00 06    ...@....^ 0.r...
0030: 00 40 11 88 bf 1f 33 00 10 00 a5 33 8d 00 80 00    .@....3....3....
0040: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
0050: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
0060: 00 00 00 00 00 00 00 00 00 0a 44 40 00 00 00 00    ..........D@....
0070: 03 23 13 01 10 10 00 00 b0 95 69 d5 99 a5 e6 f9    .#........i.....
0080: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
0090: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
00a0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00b0: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
00c0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00d0: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 f9    ..........i.....
00e0: 00 40 80 50 c0 90 54 a0 b0 95 69 d5 99 a5 e6 f9    .@.P..T...i.....
00f0: 00 00 00 00 80 00 00 00 b0 95 69 d5 99 a5 e6 0c    ..........i.....
=> i2c md 0x50 0x00 0x100
0000: 03 04 07 20 00 00 00 00 00 00 00 03 64 00 0a 64    ... ........d..d
0010: 00 00 00 00 57 54 44 20 20 20 20 20 20 20 20 20    ....WTD         
0020: 20 20 20 20 00 00 1c ad 52 54 58 4d 32 32 38 2d        ....RTXM228-
0030: 34 30 32 20 20 20 20 20 31 2e 30 20 05 1e 00 77    402     1.0 ...w
0040: 00 1a 00 00 46 52 31 38 30 31 32 38 36 38 34 20    ....FR180128684 
0050: 20 20 20 20 31 38 30 31 30 39 20 20 68 f6 03 fc        180109  h...
0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
0070: ff ff ff ff ff ff ff ff ff ff ff 80 91 a2 b3 ff    ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
=>

regards,

Robin Liu

0 Rodrigo Natal over 4 years ago in reply to Robin Liu

TI__Mastermind 19235 points

Hi robin,

The retimer values for SFP+ AOC also look good:

channel register 0x02 = 0xDC -> CDR is locked, EQ adapted
0x27 = 0x2E -> the retimer horizontal eye opening is 0.71UI
0x28 = 0x5E -> the retimer vertical eye opening is 293.75mV

At this point I don't think the retimer is the problem.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 Paul Yeh over 4 years ago in reply to Rodrigo Natal

TI__Genius 16175 points

Natal,

I compared these two txt file and find SFP+AOC REG0x52 value is 00, not 80 as SFP+DAC cable.

So is it possible the reason why fail in AOC cable?

And could you also let us know the min/max specification about HEO & VEO? And why you said HEO and VEO are ok ?

Thanks

0 Rodrigo Natal over 4 years ago in reply to Paul Yeh

TI__Mastermind 19235 points

Hi,

CTLE = 0x00 is a good value for SFP+ AOC, as the channel insertion loss is lower for AOC compared to DAC.

See below TI's recommended minimum values for the retimer eye opening values:

HEO greater or equal to 0.4UI
VEO greater or equal to 200mV

Regards,

Rodrigo Natal

Interface

Interface forum

DS110DF111: SPF + AOC can't established