SN65DPHY440SS: Is Suitable considering low MIPI clock and lengthy cable:

Will be placing the SN65DPHY440SS after 35cm cable length and Near to MIPI DSI sink (LCD).

Hi,

The DPHY440 can not support clock frequency below 100MHz and its functional behavior at below 100MHz can not guaranteed.

If using the DPHY440, I would agree with your response that the DPHY440 needs to be placed after the 35cm cable so the DPHY440 can compensate for the 35cm cable loss.

The DPHY440 can be operated stand-alone. If needed, it can also be operated in I2C mode.

Thanks

David

Thanks for the details,

Here just a quick question, as per 320x480 LCD resolution (262k color depth, Will be using single Data Lane only) configuration we done rough calculation, which was less than 100MHz.

Here MIPI clock (100MHz) has to be Bit clock as per calculation or Byte clock?

1) Is it ok if we drive that LCD with higher clock = 250MHz, (which is supported by LCD controller)?

2) Do you have any calculation reference for MIPI clock frequency? So that we can confirm our required operating freq.

3) Instead of this is it possible to use an LVDS differential buffer IC for this MIPI signals?

Hi,

What is the refresh rate for this resolution?

So the calculation is

Pixel Clock Frequency = Total Horizontal Samples * Total Vertical Lines * Refresh Rate

Total Data Rate (Bandwidth) = Pixel Clock Frequency * Pixel Size (in bits). Pixel Size is 18-bits for 262k color depth.

Data Rate per Lane = Total Data Rate (Bandwidth) / Number of Data Lane

MIPI Bit Clock Frequency = Data Rate per Lane / 2

Thanks

David

OK Thanks for the details calculation referecne.

David,

1) Can you also help me to derive the Total Pixel freq considering the following LCD configuration. 

- Pixel pitch: 0.0286x0.0286mm

- Active Area: 27.456 x 41.184mm

- Resolution: 320 x RGB x 480

- Size: 1.95inch

- MIPI Data Lane: 1

2) What is the minimum freq used for this DPHY440?

Hi,

Do you know what is the refresh or frame rate for this LCD? 

Assume frame rate is 60Hz

Pixel frequency = 320 x 480 x 60 = 9.216MHz

Total data rate = 9.216 * 18 = 165.888Mbps

Data rate = 165.888Mbps

MIPI clock frequency = data rate / 2 = 82.944MHz

So it appears that with 60Hz frame rate, the MIPI clock frequency is below the DPHY440 minimum clock frequency requirement.

Thanks

David

Yes, David. LCD frame rate is 60Hz.

But as per processor driver calculation. It doesn't mention to divide the data rate /2 considering DDR.

So, overall calculation was as below:

Total pixel clock= (Hz active+Hz front porch+ Hz back porch+ Hz Sync length) x (Vt active+Vt front porch+ Vt back porch+ Vt Sync length) x 60

Hz= Horizontal and Vt = Vertical.

Total Pixel clock= (320+38+100+4) x (480+8+8+4) x60

Total Pixel Clock= 13.86MHz

Total data lane=1 and bit per pixel =18 so.

Total Data rate = 13.86 x 18 = 249.48Mbps,

MIPI clock= 249.48MHz (considering not deviding by 2 for DDR)

Or else MIPI clock= 124.74MHz (If devided by 2)

Which comes above 100MHz, So we are considering the DPHY440 solution. Do you see any issue in above calculation?

Hi,

The calculation is correct.

Thanks

David

HI DAVID,

Thanks for your support,

As we have only 1 data lane in MIPI DSI, Can we use DATA lane 02 of DPHY440? or is it must to use Data lane 0 only.