DP83867IS: DP83867ISRGZT connection with FPGA

Hi Fabio,

1. Yes, the SGMII signal is continuous irrespective of link.

2. Clock for SGMI is derived from internal PLL

3. No change on the clock

4. It shall be inline with SGMII spec requirements.

Regards,
Geet

Hi Geet,

Can you clarify below points?

point 2: Which clock is this revived from? The local clock input or a received (network derived?) clock?

point3: Does this mean that there is no change at all (including phase / missing cycles etc?)

Regards,

Fabio

Hi Fabio,

SGMII  is running on the internal PLL clock. If you use RGMII, then it runs on recovered clock.

Point 3 : Under what condition you are referring to phase/missing cycles ?

Regards,
Geet

On point 3:

If a network connection is made or removed.

Regards,

Fabio

SGMII clock is generated from internal PLL and remains fixed. However if SGMII is used in Auto-Negotiatio mode, MDI side link drop and link up will trigger SGMII to perform auto-negotiation to synchronise with line. 

Alternatively you can look at using force mode

Regards,
Geet

Hi Geet,

Below the update:

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We have purchased some development boards for the Phy, and initial investigations show that on the SGMII clock out

1)      We have a 125MHz clock not 625MHz

2)      It disappears when we remove the network connection

The board may be configured incorrectly – we are investigating – but this is not what we expected!

Any guidance or help would be appreciated.

Hi,

Kindly provide the pin you are probing the clock.

Also, have you confirmed board is configured for SGMII and not RGMII.

Regards,

Geet