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Hello Alan,
when using the 12bit HF mode, the devices require minimum PCLK = 37.5MHz. Are you applying this CLK ?
No Hamzeh, I was relying on the internal PCLK oscillator described in 7.4.4 of the datasheet.
Hello Hamzeh,
Yes, I added an oscillator to my PCA and fed it into PCLK. All the outputs are now valid. Thank you for pointing me in the right direction. I'm happy the architecture concept is still valid for my application. I suggest requesting an addition to the datasheet in 7.4.4 to note that the parallel data is invalid in the internal oscillator mode.
Thank you!