Hi, Staff
What is the delay in using two?
We plan to configure the system with MIPI 2-port x 4-Lane.
Use two DPHY440s in your system configuration.
The ideal Skew between two chips is "0".
Is it possible to present Skew specification data between two chips?
Delay Spec in the data sheet
The maximum Skew between two chips is 28ns (40ns-12ns = 28ns).
For example, when used under the conditions of Ta = 25℃ and VDD1.8V,
Isn't the Delay Spec changed from Min.[4UI + 12ns] and Max.[4UI + 40ns]?
best regards
cafain
