DP83848Q-Q1: Reset Pin parmeters and behavior

Ralf Eckhardt

Part Number: DP83848Q-Q1

Hello,

some questions about the reset pin.

1.) The DS says : The DP83848x includes an internal power-on reset (POR) function and does not need to be explicitly reset
for normal operation after power up. If required during normal operation, the device can be reset by a
hardware or software reset. --> The DS says in the pin description I, PU. In this case it should be output as well , right ? We see that the PHY is driving the pin low.

2.) What is the value of the Pull Up on the reset Pin. I cannot find any specification.

3.)Is this specification out of the DS also valid for the Reset Pin ?

Thanks and BR Ralf

over 5 years ago

0 Nikhil Menon over 5 years ago

TI__Genius 11725 points

Hi Ralf,

We are looking into this issue and will provide an update by the end of the week.

Thank you,

Nikhil

0 Nikhil Menon over 5 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Ralf,

We are looking into the test data to confirm the exact PU value. You can estimate that it is ~10 - 50k. We are also looking into reset functionality in lab to confirm whether this should be labeled an IO. We will provide an update by early next week.

Thank you,

Nikhil

0 Nikhil Menon over 5 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Ralf,

Based on the test data, this pin should be a 27k Input.

Thank you,

Nikhil

0 Ralf Eckhardt over 5 years ago in reply to Nikhil Menon

TI__Intellectual 855 points

Hello Nikhil, this is answering point 2 of my question, but point 1and three is still open.

Can you please confirm if my assumption on point 1 is right and provide the input specification voltage levels etc. for the reset pin ?

Thanks and Br Ralf

0 Ralf Eckhardt over 5 years ago in reply to Ralf Eckhardt

TI__Intellectual 855 points

Any update on this topic ?

0 Nikhil Menon over 5 years ago in reply to Ralf Eckhardt

TI__Genius 11725 points

Hi Ralf,

Sorry for the delay. We are still looking into this issue. Due to Covid restrictions, there is limited access to labs to test reset functionality. I will provide an update by Friday.

Thank you,

Nikhil

0 Nikhil Menon over 5 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Ralf,

I am not able to reproduce this phenomenon in lab. I have placed a probe on the reset pin of the DP83848, performed a software reset, and I am not able to observe the reset pin being driven low. What setup are you using?

Thank you,

Nikhil

0 Ralf Eckhardt over 5 years ago in reply to Nikhil Menon

TI__Intellectual 855 points

Did you add a pull up to VCC on the reset Pin and did you log behavior from Power Up ?

0 Nikhil Menon over 5 years ago in reply to Ralf Eckhardt

TI__Genius 11725 points

Hi Ralf,

Yes Reset pin is pulled to VCC upon power up. Introducing a software reset does not force reset low. I can double-check tomorrow.

Thank you,

Nikhil

0 Nikhil Menon over 5 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Ralf,

We are unable to recreate this scenario in lab. While probing the reset pin and observing reset pulled high during power up and stay high during normal operation, we do not see the PHY drive the reset pin low during a software reset.

Thank you,

Nikhil

0 Nikhil Menon over 5 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Ralf,

As this discussion is being driven offline, I will be closing this thread.

Thank you,

Nikhil

Interface

Interface forum

DP83848Q-Q1: Reset Pin parmeters and behavior