TUSB1310 PHY_RESETN

MASAO YAMAZAKI

Prodigy 130 points

Other Parts Discussed in Thread: TUSB1310

Hi,

I want to know the detail of PHY_RESTEN pin function.

During RESETN pin is de-asserted and PHY_RESETN pin is asserted , is TUSB1310 outpytting PCLK & ULPI_CLK signals?

Best regards,

over 14 years ago

0 Wes Ray over 14 years ago

TI__Intellectual 2995 points

This pin is the PIPE RESET signal as defined in the PIPE spec, it is an interface level reset not a chip level reset. It just resets the PIPE transmitter and receiver.

0 MASAO YAMAZAKI over 14 years ago in reply to Wes Ray

Prodigy 130 points

Thank you for your quick reply.

In the Figure of the PIPE spec "section 6.2 Reset", it is decribed that "PCLK running at any frequency less than or equal to final operational frequency".

My understanding is that "PHY continue to output the PCLK signal during Reset# is asserting".

I want to confirm that this is corret.

And I have one more question.

In the PIPE spec "section 6.1 clocking", it is described that "This clock (PCLK) may also have spread spectrum modulation."

Is the PCLK output of TUSB1310 modulated by SSC?

I'm reading the TUSB1310 Data Manual, but I don't understand it well.

Best regards,

0 Wes Ray over 14 years ago in reply to MASAO YAMAZAKI

TI__Intellectual 2995 points

Yes, PCLK continues to run when PIPE_RESETN is asserted low. This is done purposely so that reset logic within the DL can transition.

In a USB3 application, the PHY will normally apply SSC to its own PLL so as to modulate the output data stream. This shows up on the PIPE PCLK, as it is derived directly from the PLL clock. So, if you have SSC turned on, this will also be on the PCLK.

0 MASAO YAMAZAKI over 14 years ago in reply to Wes Ray

Prodigy 130 points

HI, Ray

Thank you very much for your reply.

I understood.

Best regards,

Interface

Interface forum

TUSB1310 PHY_RESETN