SN65LV1224B: SN65LV1224B Error Issue

Wenting Wu

Part Number: SN65LV1224B

Hello Sir,

One of my customers met error issue of SN65LV1224B. Do you mind helping on a view?

There are two kinds of error phenomena: 1) the lock signal is high; 2) the lock signal is low, but the data is wrong;
2. Customer uses SERDES for inter-board communication, SERDES only transmits communication packets, without an attached clock;
3. Tried to modify TCLK_R/F, this is the result after modification, it is worse before modification;
4. The TX and RX differential pairs have been checked, and the wiring has equal length rules;
5. The conditions are limited and it is impossible to observe the differential signal of transmission;

Customer expect:
1. Locate the error problem;
2. Solve the error code problem through software, or reduce it to a minimum;
3. More details or precautions for chip usage and configuration;
4. Provide more reliable design guidance;


Best regards,
wenting

over 4 years ago

0 Wenting Wu over 4 years ago

TI__Intellectual 2355 points

Hello anyiam,

It's known that the post is assigned to you. Thanks for your supports in advanced.

Here are two more information added:

1. REFCLK is 60MHz and it's sent by another platform board.

2. The customer can not see 8b/10b later data so they can not make sure which data can cause unlock,

Here are 2 more questions from customer:

1. when unlock or error issue, are there some methods to recover?

2. Are there any other methods to locate unlock or error? can it only be observed by using oscilloscope to see serial data？

Best regards,

wenting

0 Ikechukwu Anyiam over 4 years ago in reply to Wenting Wu

TI__Mastermind 35130 points

Hi Wenting,

Can customer check the timing parameters of their REFCLK:

The ±100 ppm Frequency Tolerance spec is especially important.

Initialization (see page 3 of datasheet) should also be done.

1. The deserializer should be able to lock to random data. Sending sync patterns for resynchronization can also be done (see SYNCHRONIZATION MODE section of datasheet on page 3).

2. Only the LOCK# pin and observing data on scope are methods to know whether or not there is unlock error.

Regards,

I.K.

0 Wenting Wu over 4 years ago in reply to Ikechukwu Anyiam

TI__Intellectual 2355 points

Hello I.K,

Thanks for your quick reply.

May I ask one more questions?

When communicating between boards, can we use the local clock to decode without using the clock associated with the channel? How big is this impact?

Best regards,
wenting

0 Ikechukwu Anyiam over 4 years ago in reply to Wenting Wu

TI__Mastermind 35130 points

Hi Wenting,

Do you mean using a different clock other than RCLK on the deserializer to sample the DOUT output data? That depends on how tolerant whatever is receiving the data from the deserializer is, as there will be skew between the different clocks.

Regards,

I.K.

0 Wenting Wu over 4 years ago in reply to Ikechukwu Anyiam

TI__Intellectual 2355 points

Hello I.K,

Please see attached block diagram. Can it be realized or are there a group of CLK needed?

Best regards,

wenting

0 Ikechukwu Anyiam over 4 years ago in reply to Wenting Wu

TI__Mastermind 35130 points

Hi Wenting,

That should be fine as the 1023 will send an embedded clock on the LVDS output.

Regards,

I.K.

0 Wenting Wu over 4 years ago in reply to Ikechukwu Anyiam

TI__Intellectual 2355 points

Hello I.K,

May I ask how can we set up the Embedded CLK?

Best regards,

wenting

0 Ikechukwu Anyiam over 4 years ago in reply to Wenting Wu

TI__Mastermind 35130 points

Hi Wenting,

This information is in the datasheet - please reference page 3.

Regards,

I.K.

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SN65LV1224B: SN65LV1224B Error Issue