DP83TC811R-Q1: What is the delay between SFD symbol on the line and the assertion of the GPIO pins for IEEE 1588 indication pulse

Hi Luke,

We are looking into this issue and will provide a response by early next week.

Thank you,

Nikhil

Hi Luke,

The delay timings are as follows:

Transmit: Bit sequence 0b1101101000 to SSD symbol on MDI; min is 401ns, max is 440 ns.

Receive: SSD symbol on MDI to SFD comprising bit sequence 0b1101101000; min is 582 ns, max is 643 ns.

Thank you,

Nikhil

Hi Nikhil

Thank you for the response.

Can you confirm these numbers are related to the physical GPIO pins outputting the IEEE 1588 indication pulse? The numbers provided are alarmingly high and use of the GPIO pins is limited if this is the uncertainty range.

Regards

Luke

Hi Luke,

We are looking into this issue and will provide feedback by Friday.

Thank you,

Nikhil

Hi Luke,

We are still looking into the test data. I will provide an update when I have new information.

Thank you,

Nikhil

Hi Luke,

Thank you for your patience. 

Yes SFD detection will come after RX_DV assertion. On receive path once PCS detects 0x5D/0xD5, as indicated by register 0x4A0 Bit[13], it signals RX SFD after a configurable delay. Meanwhile RX_DV on MAC is asserted on preamble itself. There is ~300ns of delay from RX_DV to SFD indication, though this is not a guaranteed number.  

I hope this answers your question.

Thank you,

Nikhil

Hi Nikhil,
I am Luke's colleague and also involved in this project. I have a few follow-up questions please:
1) What is the expected range of uncertainty of the "~300ns" delay?
2) What is the purpose of adding a dedicated hardware pin if the accuracy appears to be no better than what can be obtained via the MAC interface?
3) Can you please similarly comment on the behaviour of the TX pin?

Best Regards,
Pierre

Hi Pierre,

We are looking in to your follow-up questions and will provide an update by Friday.

Thank you,

Nikhil

Hi Pierre,

To answer your follow-up questions:

1. The expected range of uncertainty is roughly ~300ns +/- 20%

2. Adds user flexibility

3. Will double-check TX latency and get back to you. Expected delay between TX SFD and TX_EN will be larger than TX latency.  

Thank you,

Nikhil