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Original question:

SN65DSI86: SN65DSI86: "[drm:ti_sn_bridge_probe] *ERROR* could not find any panel node"

SN65DSI86: SN65DSI86: "[drm:ti_sn_bridge_enable] *ERROR* Link training failed, link is off"

ysato
Prodigy 20 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi


https://e2e.ti.com/support/interface/f/138/t/936146

It is a continuation from.

I made the settings on i2c and was able to display the color bar.

However, SN65DSI86 ends up with Link training failed.

On my board, TEST2 is fixed at LOW and cannot be changed.

I don't display it on the eDP panel.

Display on a Full HD Monitor with a normal Displayport interface.


Does Link training fail because I haven't disabled ASSR?

Is it possible to display on a normal Displayport interface monitor even when ASSR is enabled?

  • 0
    TI__Guru**** 162006 points

    Hi,

    Link training failure is a separate issue from the ASSR. 

    If the monitor does not support ASSR, then ASSR must be disabled.

    DSI86’s ASSR will need to be disabled by making ASSR_CONTROL read/write instead of read-only. The first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:
    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    On the link training failure, does register 0xF8 report the particular error associated with the link training?  Signal integrity issue may be a cause of the failures. It may be necessary to reduce eDP data rate and/or reduce the number of DP lanes to correct link training issues. It also may be necessary to change DSI86’s Link Training Look-Up-Table default values. The LT LUT is located from register 0xB0 thru 0xC3. The LT LUT contains transmit voltage swing level and pre-emphasis levels used during the link training process.

    Thanks

    David