• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 762 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DS110DF410EVM: Help with programming on board DS110DF410 for synchronous PRBS31 output at 10.5GHz from 656.25MHz

DS110DF410EVM: PRBS output at correct datarate but I lose CDR lock when changing DIV_SEL

Sean Suttie
Intellectual 265 points
Part Number: DS110DF410EVM
Other Parts Discussed in Thread: DS110DF410

Hi all,

For my setup at the moment I have a 644.53125MHz input into the DS110DF410EVM PRBS on one channel through SMA and output as 10.3125MHz. This channel is setup as below.

I use this setup with the register set below to program the card.

When I have address 0x18 set for divide by 8 or 16 the CDR can lock and I see PRBS data out from the device at the lower datarates.

However when I set 0x18 to divide by 1 and use 0x09 set of DIV_SEL to make this change I see PRBS data out but the CDR lock is lost.

Do you understand why this may be happening? Please find the channel register set below.

   {0x00, 0x00, 0xFF},
   {0x01, 0x00, 0xFF},
   {0x02, 0xDC, 0xFF},
   {0x03, 0xA5, 0xFF},
   {0x04, 0x00, 0xFF},
   {0x05, 0x00, 0xFF},
   {0x06, 0x00, 0xFF},
   {0x07, 0x00, 0xFF},
   {0x08, 0x00, 0xFF},
   {0x09, 0x20, 0xFF},
   {0x0A, 0x10, 0xFF},
   {0x0B, 0x0F, 0xFF},
   {0x0C, 0x08, 0xFF},
   {0x0D, 0x20, 0xFF},
   {0x0E, 0x93, 0xFF},
   {0x0F, 0x69, 0xFF},
   {0x10, 0x3A, 0xFF},
   {0x11, 0x20, 0xFF},
   {0x12, 0xA0, 0xFF},
   {0x13, 0x30, 0xFF},
   {0x14, 0x00, 0xFF},
   {0x15, 0x10, 0xFF},
   {0x16, 0x7A, 0xFF},
   {0x17, 0x36, 0xFF},
   {0x18, 0x40, 0xFF},
   {0x19, 0x23, 0xFF},
   {0x1A, 0x00, 0xFF},
   {0x1B, 0x03, 0xFF},
   {0x1C, 0x24, 0xFF},
   {0x1D, 0x00, 0xFF},
   {0x1E, 0x99, 0xFF},
   {0x1F, 0x55, 0xFF},
   {0x20, 0x00, 0xFF},
   {0x21, 0x00, 0xFF},
   {0x22, 0x00, 0xFF},
   {0x23, 0x40, 0xFF},
   {0x24, 0x00, 0xFF},
   {0x25, 0x00, 0xFF},
   {0x26, 0x00, 0xFF},
   {0x27, 0x3E, 0xFF},
   {0x28, 0x9C, 0xFF},
   {0x29, 0x40, 0xFF},
   {0x2A, 0x30, 0xFF},
   {0x2B, 0x00, 0xFF},
   {0x2C, 0x72, 0xFF},
   {0x2D, 0x80, 0xFF},
   {0x2E, 0x00, 0xFF},
   {0x2F, 0x06, 0xFF},
   {0x30, 0x0A, 0xFF},
   {0x31, 0x20, 0xFF},
   {0x32, 0x11, 0xFF},
   {0x33, 0x88, 0xFF},
   {0x34, 0xBF, 0xFF},
   {0x35, 0x1F, 0xFF},
   {0x36, 0x31, 0xFF},
   {0x37, 0x00, 0xFF},
   {0x38, 0x00, 0xFF},
   {0x39, 0x00, 0xFF},
   {0x3A, 0xA5, 0xFF},
   {0x3B, 0x00, 0xFF},
   {0x3C, 0x00, 0xFF},
   {0x3D, 0x00, 0xFF},
   {0x3E, 0x80, 0xFF},
   {0x3F, 0x00, 0xFF},
   {0x40, 0x00, 0xFF},
   {0x41, 0x01, 0xFF},
   {0x42, 0x04, 0xFF},
   {0x43, 0x10, 0xFF},
   {0x44, 0x40, 0xFF},
   {0x45, 0x08, 0xFF},
   {0x46, 0x02, 0xFF},
   {0x47, 0x80, 0xFF},
   {0x48, 0x03, 0xFF},
   {0x49, 0x0C, 0xFF},
   {0x4A, 0x30, 0xFF},
   {0x4B, 0x41, 0xFF},
   {0x4C, 0x50, 0xFF},
   {0x4D, 0xC0, 0xFF},
   {0x4E, 0x60, 0xFF},
   {0x4F, 0x90, 0xFF},
   {0x50, 0x88, 0xFF},
   {0x51, 0x82, 0xFF},
   {0x52, 0xA0, 0xFF},
   {0x53, 0x46, 0xFF},
   {0x54, 0x52, 0xFF},
   {0x55, 0x8C, 0xFF},
   {0x56, 0xB0, 0xFF},
   {0x57, 0xC8, 0xFF},
   {0x58, 0x57, 0xFF},
   {0x59, 0x5D, 0xFF},
   {0x5A, 0x69, 0xFF},
   {0x5B, 0x75, 0xFF},
   {0x5C, 0xD5, 0xFF},
   {0x5D, 0x99, 0xFF},
   {0x5E, 0x96, 0xFF},
   {0x5F, 0xA5, 0xFF},
   {0x60, 0x90, 0xFF},
   {0x61, 0xB3, 0xFF},
   {0x62, 0x90, 0xFF},
   {0x63, 0xB3, 0xFF},
   {0x64, 0xFF, 0xFF},
   {0x65, 0x00, 0xFF},
   {0x66, 0x00, 0xFF},
   {0x67, 0x20, 0xFF},
   {0x68, 0x00, 0xFF},
   {0x69, 0x0A, 0xFF},
   {0x6A, 0x44, 0xFF},
   {0x6B, 0x00, 0xFF},
   {0x6C, 0x00, 0xFF},
   {0x6D, 0x00, 0xFF},
   {0x6E, 0x00, 0xFF},
   {0x6F, 0x00, 0xFF},
   {0x70, 0x03, 0xFF},
   {0x71, 0x20, 0xFF},
   {0x72, 0x00, 0xFF},
   {0x73, 0x00, 0xFF},
   {0x74, 0x00, 0xFF},


   {0x18, 0x00, 0xFF},
   {0x09, 0x24, 0xFF},
   
   
   {0x1E, 0x10, 0x10}, /* Set Bit 4 */
   {0x30, 0x00, 0x08}, /* Clear bit 3*/
   {0x30, 0x08, 0x08}, /* Set bit 3*/
   {0x0D, 0x20, 0x20}, /* Set bit 5 */
   {0x09, 0x20, 0x20}, /* Set bit 5 */
   {0x1E, 0x80, 0xE0}, /* Write 0x04 to bits 7:5 */
   
   {0xFF, 0xFF, 0xFF},

Thanks,

Sean.

  • 0
    TI__Mastermind 19235 points

    Hi,

    If you keep your current settings except that you set channel registers 0x60 thru 0x63 all to 0x00 and set 0x09[2]=0, are you able to see CDR lock to 644.53125MHz input signal? If CDR lock is observed, if you then enable PRBS generator on this retimer channel what data rate do you observe?

    Regards,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Intellectual 265 points

    Hi Rodrigo,

    Thanks for your comment.

    I attempted this experiment and I do not see the CDR lock.

    However I do still see PRBS data out but it is slightly less than 10.3125GHz (which it was around about before) the output PRBS datarate appears to drop to around 10.1GHz.

    Thanks,

    Sean.

  • 0 in reply to Sean Suttie
    TI__Mastermind 19235 points

    Hi Sean,

    Something doesn't sound right. If the CDR is not locked, you would not be able to see any PRBS data output from the retimer. The only way to see data out of retimer with its CDR unlocked is CDR bypass raw data mode. It is not possible to simultaneously select raw mode and PRBS generator as they involve separate output mux settings.

    The settings for PRBS generation captured in the TI programming have been evaluated extensively by TI; it should work.

    www.ti.com/.../snla323.pdf

    Have you tried using the TI SigCon Architect GUI to configure CDR rate and perform the PRBS generator configuration?

    www.ti.com/.../SIGCONARCHITECT

    Regards,

    Rodrigo

  • 0 in reply to Rodrigo Natal
    Intellectual 265 points

    Hi Rodrigo,

    Thanks again for your reply.

    I have been trying a mix of the sigcon tool and register programming and have had no success with any of these modes.

    I have tried all kinds of registers etc to try and get this to work and I'm not sure what I might be doing wrong.

    I can achieve CDR lock and get PRBS data out but the PRBS data is of the wrong data rate. The data that comes out is at the same rate as the clock I put in.

    What I am looking to achieve is to take the input clock that I have and generate PRBS at a 16th of this rate (input is 656.25MHz/644.5315MHz and outputs PRBS data at 10.5GHz/10.3125GHz).

    I don't see any way in the SigCon tool to change my register values to achieve this, the only way I can find to get the output data to be at the 10.5/10.3125GHz frequency is through low level register changes in the SigCon tool using the DIVSEL_OV register setting (setting 0x09 bit 2 and 0x18 bit 6:4).

    Is there anyway that you know which can allow me to generate a PRBS output from an input clock that is 16 times the clock rate?

    Thanks,

    Sean.

  • 0 in reply to Sean Suttie
    TI__Mastermind 19235 points

    Hi Sean,

    The TI retimer does indeed support PRBS output from input clock signal that is divide by 16. This is a very common use case. The SiCon Architect GUI has a "Tx DEM/PRBS generator" tab that does all of the configuration for you. Have you tried using it? You should be able to enable PRBS generator via this GUI PRBS page. If your input signal is 644.5315MHz and you keep the CDR rate setting (channel 0x2F) at default the output should be 10.3125G when PRBS is enabled via GUI.

    Cordially,

    Rodrigo

  • 0 in reply to Rodrigo Natal
    Intellectual 265 points

    Hi Rodrigo,

    Thanks for continueing to assist me on this. I have documented some of my attempts to run the SigCon tool to get PRBS data out.

    I start with the SigCon tool.

    ATTEMPTED TO LOAD PICTURES INTO MY POST BUT I WAS UNABLE.

     

    I apply the DS110DF410 configuration. To note I intend to program all channels but I am only scoping one channel.

     

    SigCon Architect File Script Device Device 1 0 Configuration Help SigCon Architect DDemo Mode *'When in Demo Mode, click •Appty• on the profile Configuration Page to enable access to other pages 0 Low Level Page 0 High level Page 0 Eye Monitor Page O LMH1218 0 Configuration Low Level Page High level Page Eye Monitor Page IOOFIII 0 Configuration Low Level Page Eye Monitor Page EEPROM Page High level Page O OS1100F410 Confi uration 0 Low Level Page 0 Eye Monitor Page O EEPROM Page 0 High level Page Device Model DSI IODF410 # ofChannels Slave Address USB2ANY Details US82ANY O Toggle LED DS110DF410 DS110DF410 Datasheet: SNLS397 DS110DF410EVK User's Guide: SNLU126 Low Power Multi-Rate Quad Channel Retimer • Each Channel Independently Locks to Data Rates from 8.5 to 11.3 Gbps and Subrates Support for Subrates of Divide-by-2/4/8 Fast Lock Operation Based on Protocol-Select Mode Low Latency t 300 ps) Adaptive Equalization up to 34-dB Boost at 5 GHz Adjustable Transmit VOD: 600 to 1300 mVp-p Adjustable Transmit De-emphasis to -15 dB Online Documentation Profile Version: I .0.3.0 TEXAS INSTRUMENTS

     

    I then follow the step to go straight to enabling the PRBS. By default no CDR has locked.

     

    SigCon Architect File Script Device Device 1 0 Configuration Help SigCon Architect Channel Indicator DDemo Mode *'When in Demo Mode, click •Appty• on the profile Configuration Page to enable access to other pages update Time(in_ms) Channel Select Block Diagra SD Settings Enabled OForce Enabled OF orce Disabled 9 9 Rx EQ/DFE Reset CDR All Channels Reset CDR 9 0 Low Level Page 0 High level Page 0 Eye Monitor Page O LMH1218 0 Configuration Low Level Page High level Page Eye Monitor Page IOOFIII 0 Configuration Low Level Page Eye Monitor Page EEPROM Page High level Page DS1100F410 0 Configuration 0 Low Level Page 0 Eye Monitor Page O EEPROM Pa e Select page All Channels Channel Refresh From Load From File save To File Tx DEM De-emphasis ORV SEL VOD @ 600 mv 0 700 mV 0800 mv O goo mv 01000 mv 01100 mv 01200 mv 01300 mv PR8S Generator Configurations Output Signal Select PR8S Generator Pattern Type @ 31 Enable Tx DEM / PR8S Generator INSTRUMENTS

     

    When I inspect the Scope waveform it there is no data out. But I am not expecting to see any as I have no CDR lock.

     

     

     

    So my next consideration is that I should make sure that CDR has locked

     

    I turn off the device and start to look at a fresh configuration.

     

    Programming all channels with standard Ethernet does not achieve lock on any of the channels.

     

     

    So I try my custom values to see if they will work and I can achieve CDR lock with these. Applying to all channels.

     

     

    Once this happens I can see that CDR has locked on all channels.

    I also see a raw output clock on the output of the channel I am monitoring (Channel 1). See below.

     

     

    Next I look to enable the PRBS through the tool.

     

     

    Once I do this I see the following on my scope:

     

    This is the waveform that I see out of my scope (note the time base)

     

     

    And this is the eye that I observe. Manual placement of markers shows that the eye is approximately at 1.28GHz.

     

     

    When I consider these as the outputs I don't think that this looks correct. At this point I haven't changed 0x2F so I expect it is at default settings but just to verify I check this in the tool. I observe that 0x2F is set to 0x06 which the SigCon Architect profile suggests is the default setting.

     

     

    I can also confirm that this is the case for all Channels on the device.
  • 0 in reply to Sean Suttie
    TI__Mastermind 19235 points

    Hi,

    If you keep the retimer default settings but then set channel register 0x0C[3]=0 via the SigCon Architect low-level page (to disable SBT) does its CDR lock to the 644.53125MHz input signal? I would expect to see CDR lock for this case.

    Can you confirm the GUI profile version you are using, and whether it is Profile Version 1.0.2.0.? You should be able to see it on the bottom right corner on the Configuration page.

    Cordially,

    Rodrigo

  • 0 in reply to Rodrigo Natal
    TI__Mastermind 19235 points

    Hi,

    I was able to make some lab time to check this retimer functionality on the bench. I can confirm that, for the retimer channel to lock to 644.53125MHz input clock signal, you may leave the CDR  rate setting at default but you need to disable SBT check by setting channel register 0x0C[3]=0. I am able to see CDR lock this way. Once CDR is locked, to enable 10G PRBS output via SigCon Architect you simply need to go to the PRBS generator tab, select PRBS pulldown option and pattern and click on enable button. However, in order for the PRBS generator setting to become effective you also need to click on the "Apply to Channel" button on the upper right of the GUI page. This is likely the minor step that your were missing.

    Cordially,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Intellectual 265 points

    Hi Rodrigo,

    Thank you for the help. I tried this step and saw that the data looked correct. I've adjusted the other settings to fit my needs and I've managed to get lock on the signal.

    Best regards,

    Sean.