DS90UB948-Q1: SSC modulation on LVDS output

Hello Casey,

Thanks for your fast feedback.

We will try with a CDCS501 (configure for a 0.5% spread) between our external clock and the ref clock input of the 941 and give you feedback.

Best regards,

Alexandre

Ok thanks Alexandre, 

Please let me know if further support is needed

Best Regards,

Casey 

Hello Casey,

I did some test with a signal generator. Unfortunatly, the SSC doesn't resolve our screen issue.

When i use the pattern generator (register 0x64 = 0xF1) of the 941 serialiser, i have the following results:

Internal timing with internal or external clock (0x65 = 0x04 or 0x0C) = OK

external timing with MIPI clock => OK

external timing with external clock => NOK, the display seems to move.

When i look at the LVDS channel 2 and CLOCK, i see no differences between the 3 options (delay between channel 2 and clock is the same, the HSYNC looks OK also.)

Do you know if it is possible to keep the internal timing with the MIPI video stream ?

Best regards,

Alexandre

Hello Alexandre,

In your original message I would you mentioned that using 941AS in PCLK from DSI reference clock mode was causing some screen distortions:

• If we use the MIPI clock, we are compliant with the screen requirement (30kHz modulation), but we are not compliant with FPD link jitter, which provide some lock issues and flickering 

Now are you saying that with external timing (from DSI) and external clock (also from DSI) that things are working ok?

• external timing with MIPI clock => OK

Those two things should basically be equivalent so I'm confused on what you are saying now. 

Best Regards,

Casey 

Hello Casey,

Sorry for the misunderstanding. The reason maybe that the behavior is confusing.

To summarize:

In video mode:

With MIPI clock => video almost OK, but we have some flickering due to MIPI jitter

With external or internal clock => video rendering is definitively NOK with color rendering issue. It is not possible to recognize a basic picture.

Using the pattern generator

With MIPI clock => almost ok with a very low occurence of flickering

With external clock or internal clock and external timing => NOK, the Red looks blue, in VCOM the display seems to move.

With external or internal clock and internal timing => OK with no flickering

Is it possible to keep the internal screen timing we use with the pattern generator in video mode ?

Best regards,

Alexandre

Hello Alex,

What is the MIPI DSI clock rate you are using here and what is the external REFCLK frequency that you are applying when using PCLK from external REFCLK mode? It is not possible to use internal timing in video mode (non-PATGEN). It sounds like there may be multiple issues here. One is that the DSI clock may have too much jitter as you say, but also the video timing coming from the DSI needs to be verified. 

Please see section 4.3 in this debug app note: https://www.ti.com/lit/an/snla356/snla356.pdf 

Hello Casey,

We are working on the DSI configuration of the microprocessor. We first disable the SSC clock which was enable by default. This improves the jitter, but there is still some synchronisation problem on the DSI clock which degrade the jitter.

The PCLK is 71.8 MHz, and the DSI Clock is 463 MHz

Thanks for the answer regarding the internal timing, and i will look at the debugg app which looks promising for our issue.

Hello Alexandre,

How many DSI lanes are you using? If you are trying to use PCLK from DSI clock mode, then the DSI clock should be continuous and the DSI mode should be non-burst mode. The PCLK frequency is related to the DSI input frequency with the following equation:

PCLK = fDSI*NLanes/12

So this DSI frequency sounds off. If you were using 4 lanes DSI, then the PCLK rate would be 463*4/12 = 154MHz. With 2 lanes DSI it would be ~77MHz PCLK so still off from your PCLK target. 

Best Regards,

Casey 

Hello Casey,

My mistake, our correct DSI frequency is 228MHz, i mix up with the UI.

I was able to make several measurement of the LVDS at the output of the deserialiser. And it appears we have some glitch on LVDS channel 2 when using an external clock, or the internal clock. We don't have this if we use the MIPI clock configuration.

Do you know what could lead these glitch in the serialiser configuration ?

Hi Alexandre,

Can you provide me the schematic?

Aaron