DS90UB960-Q1: Driving Strength of MIPI clock pins

Merlyn

Part Number: DS90UB960-Q1

Hi,

We are testing our DS90UB960 SubBoard to work with IMX6Q main board. We got an error that IMX6Q processor failed to receive a valid MIPI DDR clock signal.

(1)Probing MIPI CSI clock pin, we found that DATA PINs have an amplitude of 800mVpp,while CLK pins have a amplitude of 100mVpp(400Mbps lane speed).

(2)Data and clock signals have the same routing path.

My questions are:

(1)Are the driver strength of data pins and clock pins same or not?

(2)Can we enforce the drive strength of MIPI clock pins?

over 4 years ago

0 Hamzeh Jaradat over 4 years ago

TI__Guru** 107720 points

Hello Merlyn,

it looks like you have a wrong termination/settings at the input interface of your SoC.

Both amplitudes you mentioned are wrong. Normally you should have 1.2V +/-10% in LPTx mode and 200mV +/-10% in HSTx mode.

0 Merlyn over 4 years ago in reply to Hamzeh Jaradat

Prodigy 80 points

Thank you,Hamzeh.

My test results have done wrong. I used a 350MHz Oscilloscope and a SE 10x probe to do the test.

(1)Data signals are 1.2V. I used a large time display resolution to show signals, and it's LPTx level I seen.

(2)DS90UB960 is configured to be in continuous clock mode, signals I captured is in HSTx mode level because of small time display resolution.

(3)Drop of clock voltage level is related to clock speed and oscilloscope probe.

I confirmed this with MAX9286 Subboard. It's 400mVpp when MIPI Clock is 72MHz.

and almost the same level as DS90UB960 when MIPI clock is 216MHz (DS90UB960 is set to 400Mbps per lane,and MIPI clock is 200MHz).

Interface

Interface forum

DS90UB960-Q1: Driving Strength of MIPI clock pins