DP83822IF: question about the RX_CTRL signal

Hi Brian,

You are correct with regard to the RX_CRTL signaling. 

Can you describe the problem you are seeing? What MAC are you using in your application? Are you able to pass packets over the RGMII interface with or without errors? 

Regards,
Justin 

Hi Justin,
thanks for feedback. Customer:

"the Linux host (AM3358) can send Ethernet packets over the RGMII interface but does not receive/handle incoming data.

 -We connected the DP83822 (EVM) with the OSD3358 (internal AM3358) and have the Linux driver and device-tree operational.

-From the Linux host (on the OSD3358) we can send out a ping (Ethernet transmit) to my Windows laptop and the laptop does correctly respond.

-However the Linux host does not receive anything of this response or other received messages.

MAC TI AM3358: 98:5d:ad:d1:a1:e9  192.168.100.2

MAC Dell laptop: 8C:EC:4B:F0:5F:8A 192.168.100.1

eth0: flags=-28605<UP,BROADCAST,RUNNING,MULTICAST,DYNAMIC>  mtu 1500

        inet 192.168.100.2  netmask 255.255.255.0  broadcast 192.168.100.255

        inet6 fe80::9a5d:adff:fed1:a1e9  prefixlen 64  scopeid 0x20<link>

        ether 98:5d:ad:d1:a1:e9  txqueuelen 1000  (Ethernet)

        RX packets 0  bytes 0 (0.0 B)

        RX errors 0  dropped 0  overruns 0  frame 0

        TX packets 218  bytes 30054 (29.3 KiB)

        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

        device interrupt 55

debian@am3358:~$ ping 192.168.100.1

PING 192.168.100.1 (192.168.100.1) 56(84) bytes of data.

From 192.168.100.2 icmp_seq=1 Destination Host Unreachable

From 192.168.100.2 icmp_seq=2 Destination Host Unreachable

From 192.168.100.2 icmp_seq=3 Destination Host Unreachable

From 192.168.100.2 icmp_seq=4 Destination Host Unreachable

Wireshark laptop:

 When reading out DP83822 PHY register Table 37. 0x0017 RMII and Status Register (RCSR)

 PHY=01 REG=23 : IDLE READ  ACK 0000-0010-0100-1001 : Bit 9 = RGMII Enabled

 (We are not able to read out PHY registers higher than 0x001F)

 It looks like the DP83822 is in ‘MII mode’ instead of ‘RGMII mode’, because RX_CTRL behaves as RX_DV and NOT as a combination of RX_DV and RX_ER on the edges of the RX_CLK!!

Also the RX_D[0:3] never changes on the falling edge of the RX_CLK. This indicates as well that the PHY is MII mode and NOT RGMII despite BIT9 of PHY register 23 (0x0017) is 1."

regards,
Brian

Hi Brian,

Can you share the register details for register 0x0000-0x001F, 0x0467, 0x0468? You can implement the extended register access by following the steps in section 8.4.2 of the DP83822 datasheet.

Regards,
Justin 

For registers 0x0000-0x001F the values are:

 debian@AM3358:~$ sudo phyreg 01

PHY=01 REG=00 : IDLE READ  ACK 0011-0001-0000-0000

PHY=01 REG=01 : IDLE READ  ACK 0111-1000-0110-1101

PHY=01 REG=02 : IDLE READ  ACK 0010-0000-0000-0000

PHY=01 REG=03 : IDLE READ  ACK 1010-0010-0100-0000

PHY=01 REG=04 : IDLE READ  ACK 0000-0001-1110-0001

PHY=01 REG=05 : IDLE READ  ACK 1100-0001-1110-0001

PHY=01 REG=06 : IDLE READ  ACK 0000-0000-0000-1111

PHY=01 REG=07 : IDLE READ  ACK 0010-0000-0000-0001

PHY=01 REG=08 : IDLE READ  ACK 0100-1000-0000-0110

PHY=01 REG=09 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=10 : IDLE READ  ACK 0000-0001-0000-0000

PHY=01 REG=11 : IDLE READ  ACK 0001-0000-0000-0000

PHY=01 REG=12 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=13 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=14 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=15 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=16 : IDLE READ  ACK 0000-0000-0001-0101

PHY=01 REG=17 : IDLE READ  ACK 0000-0001-0000-1000

PHY=01 REG=18 : IDLE READ  ACK 0110-0100-0000-0000

PHY=01 REG=19 : IDLE READ  ACK 0010-1000-0000-0000

PHY=01 REG=20 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=21 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=22 : IDLE READ  ACK 0000-0001-0000-0000

PHY=01 REG=23 : IDLE READ  ACK 0000-0010-0100-1001

PHY=01 REG=24 : IDLE READ  ACK 0000-0100-0000-0000

PHY=01 REG=25 : IDLE READ  ACK 1000-1100-0010-0001

PHY=01 REG=26 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=27 : IDLE READ  ACK 0000-0000-0111-1101

PHY=01 REG=28 : IDLE READ  ACK 0000-0101-1110-1110

PHY=01 REG=29 : IDLE READ  ACK 0000-0000-0000-0000

PHY=01 REG=30 : IDLE READ  ACK 0000-0001-0000-0010

PHY=01 REG=31 : IDLE READ  ACK 0000-0000-0000-0000

 The extended registers will follow soon.

----------------------------------------------------

Additionally:

See below the bootstrap configuration we have set on the DP83822 EVM. Is this correct?

Name    Pin          Strap mode        EVM PU/PD Resistors    

COL        29           Mode4(default) R84=Open           R88=Open           FX_EN=0, PHY_AD0=1

RX_D0   30           Mode1(default) R71=Open           R72=Open           AN_1=1, PHY_AD1=0

RX_D1   31           Mode1(default) R75=Open           R76=Open           EEE_EN=0, PHY_AD2=0

RX_D2   32           Mode1(default) R77=Open           R78=Open           FLD_EN=0, PHY_AD3=0

RX_D3   1              Mode1(default) R80=Open           R82=Open           AN_EN=1, PHY_AD4=0

LED_0    17           Mode4(default) J10=Open/Pullup                             AN_0=1

CRS        27           Mode4(default) R53=Open           R55=Open           LED_CFG=1, LED_SPEED=0

RX_ER   28           Mode3                 R60=6K2               R66=1K96            AMDIX_EN=1, RGMII_EN=1

RX_DV  26           Mode1(default) R45=Open           R48=Open           XI_50=0, RMII_EN=0

FX_EN   AN_EN AN_1     AN_0

0              1              1              1                              10BASE-Te, Half/Full-Duplex

                                                                                100BASE-TX, Half/Full-Duplex

As far as I could tell, the dp83822 PHY kernel module does not write to registers at boot.

We will try to setup the USB-2-MDIO tool to read out the DP83822 registers.

Here is some additional information we can provide you. The OSD3358 (AM3358) still doesn’t receive (clock in) Ethernet data despite there is are rx_clk, rx_dv and rx_d[0..3] signals.

 We managed to read the PHY registers from the Linux host (phyreg):

 PHY=01 REG=00 : IDLE READ  ACK 0011-0001-0000-0000

PHY=01 REG=01 : IDLE READ  ACK 0111-1000-0110-1101

 PHY=01 REG=16 : IDLE READ  ACK 0000-0000-0001-0101

Furthermore we don’t think the DP83822 is put in RMII mode. If this is the case we expected a clock alike data signal on RX_D3 which we don’t see.

Regards,

Brian

Let me add:

register 0x0467

sudo phyreg 01 13 001F

PHY=01 REG=13 : IDLE WRITE ACK 0000-0000-0001-1111 (WROTE 31)

sudo phyreg 01 14 0467

PHY=01 REG=14 : IDLE WRITE ACK 0111-1000-0100-1001 (WROTE 1127)

sudo phyreg 01 13 401F

PHY=01 REG=13 : IDLE WRITE ACK 0100-0000-0001-1111 (WROTE 16415)

sudo phyreg 01 14

PHY=01 REG=14 : IDLE READ  ACK 0000-1110-1100-0011

And 0x0468:

sudo phyreg 01 13 001F

PHY=01 REG=13 : IDLE WRITE ACK 0000-0000-0001-1111 (WROTE 31)

sudo phyreg 01 14 0468

PHY=01 REG=14 : IDLE WRITE ACK 0111-1000-0100-1001 (WROTE 1128)

sudo phyreg 01 13 401F

PHY=01 REG=13 : IDLE WRITE ACK 0100-0000-0001-1111 (WROTE 16415)

sudo phyreg 01 14

PHY=01 REG=14 : IDLE READ  ACK 0000-0000-0000-0000

The values are as we expected for the bootstrap configuration.

Regards,

Brian

Hi Brian,

I will need time to review the data provided. I can provide feedback by 10/20. I appreciated your patience. 

Regards,
Justin 

thanks Justin.

customer has configured the analog loopback mode and placed 100 Ohm termination resistors.

The PRBS checker does not report an error count (0x001B bit[15:8]).

Hope this is the correct procedure:

0x0016 BIST control:

sudo phyreg 01 22 7110

PHY=01 REG=22 : IDLE WRITE ACK 0111-0001-0001-0000 (WROTE 28944)

PHY=01 REG=22 : IDLE READ  ACK 0111-0011-0001-0000

0x001B BIST Control & Status Reg1

PHY=01 REG=27 : IDLE READ  ACK 0000-0000-0111-1101

0x001C BIST Control & Status Reg2

PHY=01 REG=28 : IDLE READ  ACK 0000-0101-1110-1110

Regards,

Brian