PCI bus control on XIO2001

Patrick Marshall

I'm hoping someone can help a non-PCI(e) expert with a customer inquiry:

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I am using a XIO2001IZGU. I am wondering if it is possible to have an FPGA on the PCI bus that can take over the bus at start up and then give it back once it completes a set of instructions. What would you recommend for this?

The FPGA does not need to be that big as it just needs to execute a small set of instructions and only talk to one device besides the XIO.

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Seems like an obvious yes to me, so I'm hoping someone can simply point out the right section of the datasheet/implementation guide. Or is there more to it...?

thanks,

over 14 years ago

0 Patrick Marshall over 14 years ago

Intellectual 310 points

Clarification:

The customer would like to shut down all activity on the PCI bus for a predetermined amount of time. It appears that the PCI stop (pin 18) will do this. Can someone confirm that an acceptable approach would be to allow the FPGA on the PCI bus to assert STOP, then later tristate?

Or would another approach be recommended?

thanks again,

0 Elias Villegas M. over 14 years ago in reply to Patrick Marshall

TI__Guru* 76130 points

Hello Patrick,

It seems like this thread has been duplicated from different sources.

Please see the link below concerning this issue.

http://e2e.ti.com/support/interface/digital_interface/int-digital_interface/f/132/t/99195.aspx

Regards.

0 Nate over 14 years ago in reply to Elias Villegas M.

TI__Genius 11680 points

Elias,

That link leads to the internal forum post, which Patrick cannot view.

This is the thread that I linked in my internal post.

Thanks again for your help with this.

- Nate Johnson, Centralized AFA

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PCI bus control on XIO2001