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DP83867IR: RGMII RX_CLK Clock Cycle Duration

Andrey Gusev
Prodigy 30 points
Part Number: DP83867IR


Hello!

I plan to connect DP83867IR RGMII interface to my FPGA design. And I want to receive RX_CLK and RXD signals edge-aligned (without internal delay in PHY) and add 2ns shift to RX_CLK internally in FPGA by means of PLL. As I see in datasheet RX_CLK period can vary from 7.2 to 8.8 ns. In which situation RX_CLK period will be changing and is this slow process or period can change abruptly? Especially I want to understand can it cause PLL synchronization loss or lead to violations of TsetupR/TholdR timings?

Thanks.

Andrew

  • 0
    TI__Expert 7040 points

    Hi Andrey,

    The RX_CLK period limits are set by characterizing the period over the voltage and temperature range of the device, as well as part to part variation and process change over time. We do not expect the RX_CLK period to change abruptly, for each power-up the variation is small over compared to maximum and minimum specifications.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 30 points

    Hi Jusin!

    I use RGMII 1000BASE-T interface. I assume that RX_CLK stability is equal to PHY crystal oscillator frequency stability which is +-50ppm from datasheet requirement. So RC_CLK period can vary 7.9996..8.0004 ns due to the clock stability. It is much less then specified range 7.2..8.8 ns. How can it be?

    Regards,

    Andrey

  • 0 in reply to Andrey Gusev
    TI__Expert 7040 points

    Hi Andrey,

    The RX_CLK period specification is stated to cover a population of parts over a temperature range of -40C to 105C and a variety of voltage conditions that can have affects on the RX_CLK period. The range of 7.2ns to 8.8ns covers the variation introduced by this range of factors. The frequency stability of the RX_CLK once the device is powered and in operation will not vary are widely. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 30 points

    Hi Justin!

    RX_CLK frequency (and period) in receiving PHY is not a free parameter. It must be equal to frequency of transmit clock of transmitting PHY. And transmit clock of transmitting PHY is derived from crystal oscillator with stability +-50ppm (from datasheet). So long-term frequency of RX_CLK must be 125MHz +-50ppm for 1000Base-T. I suppose RX_CLK period can vary during initial synchronization process and can be slightly adjusted later on. And my original question was: How fast can RX_CLK period change?

    Regards,

    Andrey

  • 0 in reply to Andrey Gusev
    TI__Expert 7040 points

    Hi Andrey,

    The RX_CLK period will not change cycle to cycle when the part is in operation. As you mentioned, the frequency stability of the RX_CLK is determined by the recovered clock of the receiving PHY.

    The RX_CLK period specification is pulled from the RGMII standard, I will need to follow up with our systems team to understand if the rate the period can change is specified by the standard. I'll provide feedback in 2-3 business days. 

    Regards,
    Justin