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DS90UB960-Q1: Correct configurations for RAW12 (atleast 1 bar) Test pattern generation

Part Number: DS90UB960-Q1

My host is qualcomm 820 board which is configured as below

active width = 1920,
actv height = 1080,
line_length_pclk = 2170,
frame_length_lines = 1210
vt_pixel_clk = 78771000,
op_pixel_clk = 266666667,
fps = 30.

Currently, I am trying to generate a Test pattern from the Deserializer with the following configurations

WriteI2C(0x20,0x30)
WriteI2C(0x1F,0x02)
WriteI2C(0x33,0x03)

WriteI2C(0xB0,0x00) # Indirect Pattern Gen Registers
WriteI2C(0xB1,0x01) # PGEN_CTL
WriteI2C(0xB2,0x01)


WriteI2C(0xB1,0x02) # PGEN_CFG
WriteI2C(0xB2,0x03)


WriteI2C(0xB1,0x03) # PGEN_CSI_DI
WriteI2C(0xB2,0x2C) # RAW12


WriteI2C(0xB1,0x04) # PGEN_LINE_SIZE1
WriteI2C(0xB2,0x0B)


WriteI2C(0xB1,0x05) # PGEN_LINE_SIZE0
WriteI2C(0xB2,0x40)


WriteI2C(0xB1,0x06) # PGEN_BAR_SIZE1
WriteI2C(0xB2,0x0B)


WriteI2C(0xB1,0x07) # PGEN_BAR_SIZE0
WriteI2C(0xB2,0x40)


WriteI2C(0xB1,0x08) # PGEN_ACT_LPF1
WriteI2C(0xB2,0x04)


WriteI2C(0xB1,0x09) # PGEN_ACT_LPF0
WriteI2C(0xB2,0x38)


WriteI2C(0xB1,0x0A) # PGEN_TOT_LPF1
WriteI2C(0xB2,0x04)


WriteI2C(0xB1,0x0B) # PGEN_TOT_LPF0
WriteI2C(0xB2,0xBA)


WriteI2C(0xB1,0x0C) # PGEN_LINE_PD1
WriteI2C(0xB2,0x0B)

WriteI2C(0xB1,0x0D) # PGEN_LINE_PD0
WriteI2C(0xB2,0x93)

WriteI2C(0xB1,0x0E) # PGEN_VBP
WriteI2C(0xB2,0x40)

WriteI2C(0xB1,0x0F) # PGEN_VFP
WriteI2C(0xB2,0x40)

When I view the pattern, I get a single bar spread out to width of full screen as expected and then the application crashes. I will post the application issue on qualcomm thread, but I just wanted to be sure that my configuration for 1920x1080 @30fps RAW12 Datatype is configured correctly and there is no issue there.

Additionally, Can someone answer the following questions

-> Can we generate a 4K resolution pattern on this deserializer ? If so, Can I get the configurations for the same?

-> How do we consider the Horizontal blanking and clock speed? Or is it configured to what the host expects?

Thanks in advance,

AG

  • Hi AG,

    This is the PatGen registers you should set:

    Register Data Name
    0x01 0x01 PGEN_CTL
    0x02 0x33 PGEN_CFG
    0x03 0x24 PGEN_CSI_DI
    0x04 0x07 PGEN_LINE_SIZE1
    0x05 0x80 PGEN_LINE_SIZE0
    0x06 0x00 PGEN_BAR_SIZE1
    0x07 0xF0 PGEN_BAR_SIZE0
    0x08 0x01 PGEN_ACT_LPF1
    0x09 0xE0 PGEN_ACT_LPF0
    0x0A 0x02 PGEN_TOT_LPF1
    0x0B 0x0D PGEN_TOT_LPF0
    0x0C 0x0C PGEN_LINE_PD1
    0x0D 0x67 PGEN_LINE_PD0
    0x0E 0x21 PGEN_VBP
    0x0F 0x0A PGEN_VFP

    We do not support 4k. The horizontal blanking does not contribute to CSI bandwidth. The clock speed is configured in reg 0x1F.

    Jiashow

  • Hi Jiashow,

    Thank you for your reply.

    The configurations you have shared are default and not for 1920x1080 and RAW12 format. Could you verify ?

  • Hello,

    My apologies for the confusion. Please try the following:

    Register Data Name
    0x01 0x01 PGEN_CTL
    0x02 0x33 PGEN_CFG
    0x03 0x2C PGEN_CSI_DI
    0x04 0x0B PGEN_LINE_SIZE1
    0x05 0x40 PGEN_LINE_SIZE0
    0x06 0x01 PGEN_BAR_SIZE1
    0x07 0x68 PGEN_BAR_SIZE0
    0x08 0x04 PGEN_ACT_LPF1
    0x09 0x38 PGEN_ACT_LPF0
    0x0A 0x04 PGEN_TOT_LPF1
    0x0B 0xBA PGEN_TOT_LPF0
    0x0C 0x0A PGEN_LINE_PD1
    0x0D 0xC3 PGEN_LINE_PD0
    0x0E 0x76 PGEN_VBP
    0x0F 0x0A PGEN_VFP