Other Parts Discussed in Thread: LMH1983,
I have two different 12G SDI designs, both with an Arria 10 FPGA, LMH1983/LMK00328 generating the 297MHz reference clocks, and similar layout. The difference is one uses a GS12181 and the other an LMH1297. The 12G 100K jitter is outside the 0.3 spec at around 0.4 on the LMH1297 board and in spec at 0.22 on the GS12181 board. In order to get the 0.22 on the GS12181 I must crank down the bandwidth register. I see the LMH1297 has register 91 and 9C setting for the A10 but this does not seem to solve our 100K jitter issue only seen on the LMH1297 design. Any suggestions?
Thanks
Jason
