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DP83867IS: Debugging problems

Amy Luo
Expert 6895 points
Part Number: DP83867IS

Hi team,

Another customer asked about DP83867, sorry to disturb you again.

The customer problem is described as follows:

1. FPGA and PHY chip are connected through SGMII interface, and a PCS IP core is used in FPGA. During the test, PHY chip is configured as self loop mode, and PCS IP core has a state output signal LED_ LINK（ this signal indicates a successful link synchronization）. After downloading the program, the link and test are normal. The received data is also correct after comparison. After running the program for about 1 minute, the received data has an error. At this time, it is found that the LED will be pulled low. Under normal circumstances, it should be always high. Then, the signal will be sometimes high, sometimes low, and the received data is also wrong.

In addition, once this kind of phenomenon occurs, as long as the power is not turned off and the program is downloaded many times for testing, the error of receiving data is the same. The error of receiving data will be different only if the power is cut off and powered on again.

2. pin3 and pin9 should supply 2.5V power, but when 2.5V is not connected, there will be about 3V voltage. After connecting 2.5V, the two pins are still about 3V.

The schematic is as follows

  • 0
    TI__Genius 9920 points

    Hi Amy

    What do you mean by self loop mode? Do you mean one of our loopback modes? Also what type of receiver error are you seeing? 

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    TI__Expert 6895 points

    Hi Cecilia, Thank you for your reply.   

    Yes, the self loop mode refers to loopback modes in the DP83867 datasheet. Both digital and analog modes have been tried, and the phenomenon is the same.

    Receiving data error means that the sending part of FPGA sends a segment of hexadecimal sequence number from 0x01 to 0x49, but the data received in the receiving part has an error at a certain position, which is different from the sender.

    According to the current test situation, the general error occurs in the front part of the data, but the CRC part received later is correct. In other words, the received data is an error in a certain byte, but this error generally occurs in the front part of a frame, that is, removing the leading 15 5, One D, and then receive a few bytes, there is a certain probability that an error will occur, but the last CRC part received is correct. Because the data sent is fixed, its CRC is fixed, so you can see that the CRC part is correct.

  • 0 in reply to Amy Luo
    TI__Genius 9920 points

    Hi Amy,

    Can you share the register dump moments before you see the receive error and then also again when you see the receive error?

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    TI__Expert 6895 points

    Hi Cecilia,

    loopback mode can work. The problem is that the RJ45 VCC is connected to 3.3V，which needs to be suspended