SN65LVDS822: CPU LVDS design discussion

I will review the schematic and get back with you tomorrow.

Aaron

Hi,

When you see the leakage, what is the following pins below setting to?

CLKPOL, SLEW, MODE14, SHTDN, SWAP

Aaron

Hi user4979999,

Were you able to get the information MODE14? I would like to know what this pin is setting to. I realized that you have the series resistors in place with LVDS pins. What is the value? The series resistor on the input LVDS are intended for unused pins. You must change those to 0Ω resistor. Are you using all 4 data inputs? Can you double check if the CPU transmitting the clock?

Aaron

Hi,

See feedback below.

CH1: 1.8V

CH2: CLKPOL

CH3: MODE14

CH4: SHTDN#

Hi,

Thanks for sharing the snapshot. Can you remove the series resistors in LVDS pins and change it to 0Ω? Did you observe the same issue?

Aaron

Hi,

For MODE14 pin, you can see the waveform in last reply, it is set to low.

And the series Res is 0 ohm, CLK can output normal.

Regards,

Hi,

Thanks for confirming the series resistor is zero ohm and the waveform was taken when the series resistor is zero ohm. I will look into this and get back with you sometimes tomorrow.

Aaron

Hi,

Can you help zoom out at the circle please? I want to see why there is a spike in red circle.

Aaron

Dear Aaron:

here is the zoom in.

CH2: CLKPOL

CH3: MODE14

i think it is not a spike, it is a pulse when SW config the GPIO during this period.

Max

Hi Max,

The CLKPOL and MODE14 are input pins. These pins are supposed to be static LOW which mean you can't change these pins dynamically on the fly. The MODE14 sets the LVDS data format.

Aaron