DS90UB927Q-Q1: Reference Design of DS90UB927 and DS90UB948

Hi Sundar,

Thank you for reaching out to us. I will review the schematic and get back with you by 10/26.

Aaron

Hello Aaron,

Did you get the time to review the schematics?

Also, we have a doubt.

We were able to get the i2c address of 927 which is 0x0c using "i2cdetect" command.But we were not able to get the i2c address of 948.

Is there anyway to confirm 948 is connected properly with 927?

The connection sequence is IMX8 -> 927 -> 948

Please help us on this with priroity.

Thanks,

Sundar

Please find the i2cdump of 927

root@imx8qmmek:~# i2cdump -y 6 0x0c
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 18 00 00 d2 80 00 58 00 00 00 00 00 01 20 00 00 ?..??.X.....? ..
10: 00 00 00 14 00 00 fe 1e a1 a5 00 00 0c 00 00 00 ...?..????..?...
20: 0b 00 25 00 00 00 00 00 00 24 00 20 00 00 a5 5a ?.%......$. ..?Z
30: 03 10 00 00 00 00 08 00 00 0a 20 20 00 00 00 00 ??....?..? ....
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...............
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 ....?...........
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 b8 00 78 00 00 60 40 00 00 00 00 00 00 00 ..?.x..`@.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 b8 00 68 08 00 00 00 00 00 00 00 00 00 00 ..?.h?..........
f0: 5f 55 42 39 32 37 00 00 00 00 00 00 00 00 00 00 _UB927..........
root@imx8qmmek:~#

Hi Sundar,

I was able to review your schematic.

1. Remove R429 on UB927. This will strap the 927 to I2C address 0x18.
2. You need to strap the LPMODE to a high or low, but not floating. This pin is dictated by your PCLK.
3. Make sure you have MODE_SEL0 and MODE_SEL1 on UB948 strap correctly.

Aaron

Hello Aaron,

Thanks for your reply.

We have done the modifications as suggested. Please find the updated schematics attached with this.

Also, Please suggest why UB948 is not being detected by HOST(IMX8) using i2cdetect.

927_Update.pdf948_Update.pdf

Hi Sundar,

Can you provide me the diagram how you connect the 927 and 948 as well as the I2C? Please execute this command at the scripting tab Board.ReadI2C(0x58, 0x00).

Aaron

Hello Aaron,

After enabling I2C pass through on 927(i2cset 6 0x0c 0x03 0xDA),we were able to see the 948 i2c address using i2cdetect command. 
But we were not able to detect the slave device(Touch panel) connected with the 948.

I have tried below I2C Passthrough configurations on 927 to detect the remote slave connected with 948.

i2cset 6 0x0c 0x03 0xDA

i2cset 6 0x0c 0x17 0x9E

i2cset  6 0x0c 0x17 0x80

Please suggest to detect the i2c address of the touch panel connected with 948.

Thanks,
Sundar

Hi Sundar,

I am glad that you were able to communicate the 948 successfully. If you want to access the touch panel, you would need to connect the I2C from the touch panel to the 948. Then, you need to use the register Slave ID and Slave Alias registers 0x8 - 0x17. Each slave I2C address requires one Slave ID and Slave Alias.

Hope this helps. Let me know if you have further questions.

Aaron

Hello Aaron,

Thanks for the reply. We will check that.

Do you have DRM BRIDGE driver for fpdlink and kernel driver for UB927 and UB948?

Thanks,

Sundar

Hi Sundar,

Unfortunately, I do not have the this type of driver available.

Aaron

Hello Aaron,

We have a issue like when we configure LVDS CLK frequency as more than 30 MHZ (For example 65 MHZ) , The 948 deserializer is not recognised on the host.

We understood that 948 is accepting LVDS CLK frequency less than 30 MHZ. 

The connection sequence is HOST->927->948->LCD PANEL.

From HOST we are sending LVDS DATA with CLK 65 MHZ. In 927 it reaches as 65 MHZ. But 948 LOCK becomes 0 at that time

From HOST we are sendng LVDS DATA with CLK 25 MHZ.Now 948 gets locked with 926 and display is working.

Could you please help us on this?

Thanks,

Sundar

Hi Sundar,

Can you confirm what do you set the LFMODE to for 927?

Aaron

Hello Aaron,

LFMODE=0

MAPSEL=0

REPEAT=1

IDx=0V

BKWD=0

These are the settings of 927.

Thanks,

Sundar

Hi Sundar,

Thank you for confirming the 927 setting. Can you read the following register for 948: 0x1C, 0x37, 0x41? On your 948 board, can you also change the AC coupling cap C57 - C60 with 100nF?

Once you are done with the rework, please run the eye monitoring tool in ALP connecting to 927 and 948.

Aaron

Hello Aaron,

Thanks for the reply, Please find the I2C DUMP of 948 when LVDS CLK as 25MHZ as below.

root@imx8qmmek:~# i2cdump -y 7 0x2c
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 58 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00 X?.???.?........
10: 00 00 00 00 00 00 00 00 00 01 00 00 03 10 90 05 .........?..????
20: 00 00 40 20 08 00 83 84 00 00 00 00 00 00 00 00 ..@ ?.??........
30: 00 00 90 25 01 00 00 8a 00 00 00 3f 20 e0 23 00 ..?%?..?...? ?#.
40: 43 03 03 00 60 88 00 00 0f 02 00 08 00 00 63 00 C??.`?..??.?..c.
50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00 ??.??....? ....
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00 ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 84 00 00 00 00 00 00 00 00 00 00 00 00 00 ..?.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00 _UB948..........



As you suggested we have modified the C57-C60 cap as 0.1uF(which is 100nF). But still we were not able to get the display with 65 MHZ LVDS CLK.
Also 948 is not able to detect in i2cdetect when we set LVDS CLK as 65MHZ due to LOCK is not happening on 948.

We are not using ALP tool as we are working with Embedded Linux Host with our customized 927 and 948.

Please suggest on this.

Thanks,
Sundar

Hi Sundar,

Thanks for sharing the register dump. I am suspecting that it could be the SI performance issue. I would suggest that you need to tap on the 948 I2C if you can use ALP eye monitoring tool allowing you determine of the eye. According to your register dump, there is a linked and locked especially registers show 0x00 = 0x58, 0x07 = 0x18, and 0x1C = 0x03. Can you provide me for the following questions?

• Are you running at single or dual port? The register shows only configured for single FPD and OLDI.
• Can you get the register dump for 927 as well?

Aaron

Hello Aaron,
Thanks for the reply.

Please find the i2cdump of 927 as below:

root@imx8qmmek:~#
root@imx8qmmek:~# i2cdump -y 7 0x0c
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 18 00 00 da 80 00 58 00 00 00 00 00 05 20 00 03 ?..??.X.....? .?
10: 00 00 00 14 00 00 fe de a1 a5 00 00 04 00 00 00 ...?..????..?...
20: 0b 00 25 00 00 00 00 00 00 24 00 20 00 00 a5 5a ?.%......$. ..?Z
30: 03 10 00 00 00 00 08 00 00 0a 20 20 00 00 00 00 ??....?..? ....
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...............
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 ....?...........
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 b8 00 58 00 00 60 40 00 00 00 00 00 00 00 ..?.X..`@.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 b8 00 48 08 00 00 00 00 00 00 00 00 00 00 ..?.H?..........
f0: 5f 55 42 39 32 37 00 00 00 00 00 00 00 00 00 00 _UB927..........

Are you running at single or dual port? The register shows only configured for single FPD and OLDI.
Yes We are configuring for Single FPD and OLDI only.

Thanks,

Sundar

Hi Sundar,

I think there is a signal integrity issue here. As you mentioned on the previous that you had it working with 927 and 926 at lower rate and when you swapped the 948, you were not able to get it lock. The register dump show that you were able to get the back channel, but not forward channel. We need to look into the eye of your board. Here is what I need you to do.

1. Isolate your customized I2C on your 948 board.
2. Connect I2C USB2ANY dongle to your customized 948 SCL, SDA, and GND.
3. Run the ALP.
4. Run the eye monitoring tool to see if there is an eye meet the channel specs.

Aaron

Hello Aaron,

Sorry for the delayed response.

FYI,We have only 927 and 948 with us not 926. The 927 and 948 board which we have is our design and not EVM. and the schematics already attached in the ticket.

With 927 and 948 when we set the LVDS CLK frequency less than 30 MHZ the display is coming up properly.

If we set the LVDS CLK frequency more than 30 MHZ, display is not coming up and 948 is not being detected by HOST platform using i2cdetect tool.

As you suggested we tried to install ALP,USB2ANY software in Windows PC.

But Unfortunately USB2ANY is not being identified by ALP.

Could you please help to provide the USB2ANY firmware loader software and the firmware version to load.

Also please help to share the ALP version which is compatible with USB2ANY tool. We will try.

Thanks,
Sundar

Hi Sundar,

Let me check on this, and I will get back with you by 11/25.

Aaron

Sundar,

>>>Could you please help to provide the USB2ANY firmware loader software and the firmware version to load.

 E2E link below has the instructions for downloading firmware loader software and right firmware version to load

https://e2e.ti.com/support/interface/f/138/p/728245/2688720?

Let me know if you run into problems.

Thanks,

Vishy

Hello Vishy,

Thanks for the response, The link is useful and now we were able to see USB2ANY tool on ALP.

Hello Aaron/Vishy,

Do we have any procedure to run eye monitoring  tool using ALP? will it work with customized 948 boards?

Thanks,

Sundar

Hello Aaron,Casey,

Apart from eye monitoring , do we have any other way to identify why 948 is not accepting PCLK more than 25 MHZ?

Our oscilloscope doesnt support to do eye monitoring.

If you have any other suggestion please let us know

can we try BIST on 948 with PCLK more than 25MHZ?

Thanks,

Sundar

Hi Sundar,

In order to determine if the SI performance is good, we need to make sure that you have a good eye. If you tried with lower PCLK and able to get it working, but not higher PCLK. This telling me that you might have an issue with SI. You need to monitor the eye when you have PCLK > 25MHz.

The best way is to use the high-speed scope with SI analysis tool. The BIST is only operate locally. You need to monitor the eye coming cross the serializer to deserializer.

Aaron