Other Parts Discussed in Thread: TCAN4550,
Greetings fellows of the TCAN4550,
We have designed the TCAN4550 into our product. We have 24 TCAN channels in total. The schematic for all TCAN chips is identical.
Around 8 of the 24 TCAN chips are experiencing a weird SPI issue. Attempting to read SPI registers higher than 0xff sometimes returns 0x0. Accessing lower-address registers (ex: 0x0, 0x4, basically anything under 0x100) works reliably over a long period of time.
Every TCAN chip is located close to its level shifter. We have also tried inserting 500R SPI series termination to a channel which is malfunctioning with no improvement.
One can see here that reading 0x4 is reliable with no issues for all channels:
Reading 0x1000 is problematic for some TCANs:
Channel M0:2 is actually the channel with improved signal integrity (500R series term). SPI Signals have around 1V overshoot/undershoot with VIO = 5V. Not the greatest but definately no where near threshold levels.
The puzzling questions is: What is the difference between reading 0x1000 and 0x0004? Both bit patterns have just one bit set in the address part of the SPI read command. I can only explain this behaviour with something internal to the TCAN. All channels have identical software and SPI implementation.
Just to increase the confusion, I have noticed that the register 0xC behaves differently for the channels which are malfunctioning. Healthy channels read out 0x28000008 while unhealthy channels sometimes read out 0x28000000. This means "Internal_access_active" not being set. I cannot explain this further however.
All rails look OK.
VIO is 5V, decoupled with 1uF 0402.
VCCout has 10uF decoupling and is not driving any external loads.
VSUP is 12V.
TCANs are running in Normal mode with SWE disabled and no CAN bus connected.
The contents of 0x820 is mostly 0x4a0 (when read successfully). A single TCAN reads out 0x4004a1.
Regards,
Hussein Alasadi
