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DP83822I: Startup behavior: Should be Auto-Negotiation and Auto-MDIX but often starts in FD Mode

Josef Alt
Intellectual 1755 points
Part Number: DP83822I
Other Parts Discussed in Thread: AM4372

My customer is having trouble that DP83822I does not start up in the right mode.
According to the datasheet, it should be starting up in auto-negotiation and auto-MDIX mode. The internal PU/PD resistors are defined this way.
The PHY is connected 1:1 to the MII of the AM4372B and no additional configuration-resistors are used.

Problem is, the PHY often starts in FD mode and then does not recognize a standard 10/100M LAN cable.

Have you seen this behavior before? Any hints on how to address this issue?

We have also found this note in the data sheet:

 

Shall the RX_ER now be connected, or not? It is not exactly clear from the data sheet paragraph. In my customer's design, it is connected.

Thanks, in advance for your help

Josef

  • 0
    TI__Mastermind 26320 points

    Hi Josef,

    PHY link-up mode ( FD or Auto-Neg) is strap configurable. Can you please read and share the SOR register 0x467 and 0x468 ? 

    Regards,
    Geet

  • 0 in reply to Geet Modi
    Prodigy 70 points

    Hello Modi

    is there a way to read out these registers via Uboot or in Linux?

    I tried to read the registers in Uboot using the mii command, but the mii command only supports addresses up to 0xFF.

    Thanks!

  • 0 in reply to user6135444
    TI__Mastermind 26320 points

    Hi Josef,


    You have to use extended address space command to read the registers. I can connect you with Linux driver expert offline.

    Regards,

    Geet

  • 0 in reply to Geet Modi
    Prodigy 60 points

    Hi Josef, Modi, Geet,

    I did some more tests and it turns out that the direct connetion (100R series R´s) between AM4372´s MII and the PHY causes a problem.

    I connected a 4,7k PU to COL Pin and got correct HW init, meas the Phy starts-up not in the FX mode but 100Tx

    I disconnect the COL Signal from AM4372 (removed the 100R Series-R) and removed the ext. PU and got same result.

    I made repeated Pyh-HW Reset cycles and got same correct start-up's.

    This clearly turns out that the µC helds the COL pin low even I hold the SYSREST to low or the PU in the Phy is too weak.

    What do you recommend? I think we shall add an extra PU to COL to have the COL in a high while PHY is initialzed, even the default PHY Stappings shall be OK.

    Is there a risk that other internal strappings are too weak as well in conjunction with AM4372?

    Currently we made a work-around by SW and made a SW initialization of the PHY after start-up. This is a sub-optimal solution because we planned to load SW in teh factory by TFTP boot source function of the AM4372. In this very first moment usually there is no SW in the system and if the PYH starts in FX Mode we habe no access to the TFTP-Boot Server.

    BR

    Dieter

  • 0 in reply to Dieter Mueller
    TI__Mastermind 26320 points

    Hi,

    Default PHY strappings are ok if not influenced by MAC IOs.

    Regards,
    Geet