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DS90UR903Q-Q1: FPD link IC selection

ameenu vm
Prodigy 155 points
Part Number: DS90UR903Q-Q1
Other Parts Discussed in Thread: DS90UB914A-Q1, DS90UB913A-Q1, DS90UB913Q-Q1, DS90UB914Q-Q1, DS90UR906Q-Q1, DS90UR905Q-Q1, DS90UB925Q-Q1, DS90UB926Q-Q1

Hi all,

We are using OV426 video processor, So, it has HREF, Vertical sync pulses, P-clock signal line, I2c signals and 10 bit data bus as output or control lines to connect with FPGA. we have to recreate these signals after long run of cable. I am not sure that whether any other suitable IC rather than DS90UR903Q is available or not. Can you assist us to get suitable one for us

Thanks and Regards,

Ameenu

  • 0
    TI__Guru** 103215 points

    Hello Ameenu,

    You can use DS90UB913A-Q1 and DS90UB914A-Q1 or this link. The OV426 is parallel 10 bit DVP 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 155 points

    Hi Casey,

    Thanks for your reply..

    OV426's PCLK is 8 MHz... so, i am not sure whether those will work or not...Because DS90UB913A-Q1  and DS90UB914A-Q1  are having 25MHz to 100MHZ PCLK.

    Thanks and Regards,

    Ameenu

  • 0 in reply to ameenu vm
    TI__Guru** 103215 points

    Hello Ameenu,

    Ah ok, in that case yes DS90UR905Q-Q1 and DS90UR906Q-Q1 are probably the most suitable products from our portfolio. If the video blanking can be increased to provide at least 10MHz PCLK, then DS90UB913Q-Q1 and DS90UB914Q-Q1 could be used as well. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 155 points

    Hi Casey,

    Thanks for a suggestion

    I am bit confused. How is it compatible these parallel 10 bits data of ov426 (it gives 10 bit R data from 10 data lines at a single pulse and then B data on next clock pulse... and so on...) to these discrete 5 bits of RGB on  DS90UR905Q-Q1 ...? 

    Is there any Eval kit is available? Also can you share Reference Design files to evaluate and implement on our own board?

    Thanks and Regards,

    Ameenu 

  • 0 in reply to ameenu vm
    TI__Guru** 103215 points

    Hello Ameenu,

    The parallel 10 bits from OV426 can be connected to any of the 24 R/G/B pins on the 905/906 and unused pins can be left NC (or better tied to GND with a weak pull down to ensure that they are not toggling from noise). The 905 input R/G/B pins which are used will be the same R/G/B pins that output the data on the 906 side.  

    EVKs are no longer available for this older device but the EVK user's guide and schematics can be found here as a reference. We no longer have the original design files for the board: https://www.ti.com/lit/ug/snlu104/snlu104.pdf 

    Best Regards,

    Casey 

     

  • 0 in reply to Casey McCrea
    Prodigy 155 points

    Hi Casey,

    Thanks for better assistance..

    Please let me know whether any other IC with FPD link 3 is available or not for our suitable solution.. so that we can avoid this (DS90UR905Q-Q1) outdated one and have EVK and references to test and making on our own board.. we don't need i2c control on serializer or Deserializer ICs to program or to change register values. But we need to configure host processor through i2c. what about DS90UB925Q-Q1 ?

    Thanks and Regards,

    Ameenu

  • 0 in reply to ameenu vm
    TI__Guru** 103215 points

    Hello Ameenu,

    Yes, DS90UB925Q-Q1 and DS90UB926Q-Q1 could be used here as well in the same way as 905/906. 

    EVM boards are available in the product page 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 155 points

    Hi Casey,

    okay, I want to confirm with you on following points...,

    1. we have to control OV426 (Serializer side) from the FPGA which is from Deserializer side through I2C in real-time... we do not need to take I2C signal besides with FPD link cable for long run... These I2C signal will be handled by FPD link 3 in long cable... so that we can have only a FPD link wires  and can avoid these I2C signal lines in that cable.... isn't it right?

    2. Found in datasheet as saying that Deserializer should be placed near to target device within 1-3 inches (section 9.1.1 in DS90UR905 datasheet)... In our scenario, there is signal isolator after the Deserializer and then to custom FPGA board...if we take isolator as target device, it will be satisfied above criteria.. let me confirm with you that, is it mandatory to accord with above criteria in order to function..?

    3. Apart from FPD link updation from DS90UB925Q-Q1 over DS90UR905, is there any other difference between them? 

    Thanks for wonderful support from TI..

    Kind Regards,

    Ameenu

  • 0 in reply to ameenu vm
    TI__Guru** 103215 points

    Hello Ameenu,

    1. Yes, correct 

    2. Yes, correct. Primarily this recommendation is to ensure good signal integrity for the low speed parallel signals between DES and the target device. As long as this can be maintained so that the target device can properly sample the parallel PCLK and data bits, then it is ok

    3. 905 is part of the FPD Link II generation which uses a similar signaling scheme, but communication is unidirectional (SER to DES) on the wire only. 925 is part of the newer FPD Link III generation which supports bidirectional communication on one wire (see here for FPD Link III foundational information): https://training.ti.com/ti-precision-labs-what-is-fpd-link?context=1139747-1138099-1139854-1139837 

    Best Regards,

    Casey