Hardware configuration is as follows:
sensor–> TI DS90UB953 (serializer)--------TI DS90UB960 (deserializer)–> TX2 MIPI CSI2(4 lane)
The problem is:
TX2 failed to receive image data from MIPI CSI2 if the UB960(deserializer) 's MIPI lane bitrate is set to 1.6Gbps(1x4lane),
while everything works fine with 800Mbps MIPI lane (1x4lane).
And we also test the MIPI CSI-2 communication using 960's pattern generator,
instead of inputs from image sensors.
The same problem occurs.
So seems there is some problem with the MIPI-CS-2 interface between 960 and Jetson Tx2.
We also checked the PCB trace delay carefully, according to the 960's data sheet, "10.1.3 CSI-2 Guidelines".
And we confirm that the MIPI CSI-2 trace and layout satisfy the requirements:
- The max trace length is less than 2800mil, which is approximately less than 540ps.
- the Intra-pair length mismatch is less than 5mil, so the intra-pair skew is less than 1ps;
- the inter-pair length mismatch is less than 10mil, so the inter-pair skew is less than 5ps.
While we try to capture image on Nvidia Jetson TX2, the kernel outputs some MIPI CSI-2 related errors,
showing that there are some CRC / ECC errors in the MIPI packet.
What's the difference between 800Mbps and 1.6Gbps MIPI data rate?
Should 960's MIPI CSI-2 timing parameters be adjusted for 1.6Gbps data rate?
