• State TI Thinks Resolved
  • Locked Locked
  • Replies 12 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 1332 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI86: No signal output even when color bar mode is enabled

haitaka kanamura
Prodigy 70 points

Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi,

There is no signal output when we enabled color mode.

In our design our cpu's 4 mipi dsi lanes are connected to sn65dsi86 and sn65dsi86's 2 dp lanes are connected to TUSB546.

At first I used ti-sn65dsi86 driver in linux, but it didn't work. Then I used the generated code of SN65DSI86_PANEL_VIDEOREGISTER_CALC.xlsm. But even then there is no signal output from sn65dsi86. I also changed ML_TX_MODE to 1(normal mode) instead of semi-training mode. This didn't work either. I also disabled enhanced framing and assr.

The status register 0xF0=3 and the others are 0.

My code is based on SN65DSI86_PANEL_VIDEOREGISTER_CALC.xlsm.

    regmap_write(pdata->regmap, 0xff, 0x7);
    regmap_write(pdata->regmap, 0x16, 0x1);
    regmap_write(pdata->regmap, 0xff, 0x0);

    regmap_write(pdata->regmap, 0x11, 0x00);

    regmap_write(pdata->regmap, 0x5c, 0x01);

    regmap_write(pdata->regmap, 0x0a, 0x6);

    regmap_write(pdata->regmap, 0x10, 0x26);

    regmap_write(pdata->regmap, 0x12, 0x59);
    regmap_write(pdata->regmap, 0x13, 0x59);

    regmap_write(pdata->regmap, 0x94, 0x80);

    regmap_write(pdata->regmap, 0x0d, 0x1);
    usleep_range(10000, 15000);

    regmap_write(pdata->regmap, 0x5a, 0x00);

    regmap_write(pdata->regmap, 0x93, 0x20);

    regmap_write(pdata->regmap, 0x96, 0x1);

    usleep_range(20000, 25000);

    regmap_write(pdata->regmap, 0x20, 0x80);
    regmap_write(pdata->regmap, 0x21, 0x07);

    regmap_write(pdata->regmap, 0x22, 0);
    regmap_write(pdata->regmap, 0x23, 0);

    regmap_write(pdata->regmap, 0x24, 0x38);
    regmap_write(pdata->regmap, 0x25, 0x04);

    regmap_write(pdata->regmap, 0x2c, 0x94);
    regmap_write(pdata->regmap, 0x2d, 0x0);

    regmap_write(pdata->regmap, 0x30, 0x24);
    regmap_write(pdata->regmap, 0x31, 0x00);

    regmap_write(pdata->regmap, 0x34, 0x58);
    regmap_write(pdata->regmap, 0x36, 0x4);

    regmap_write(pdata->regmap, 0x38, 0x2c);

    regmap_write(pdata->regmap, 0x3a, 0x5);

    regmap_write(pdata->regmap, 0x5b, 0);

    regmap_write(pdata->regmap, 0x3c, 0x17);

    regmap_write(pdata->regmap, 0x5a, 0x08);

  • 0
    TI__Guru**** 189551 points

    Hi, 

    Can I take a look at your schematic? 

    Are you actually probing the DSI86 output or the TUSB546 output? 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    I am probing the DSI86 output. For now EN pin is high as soon as the ic is powered and it always remains high. TEST2 pin is pullup. We do not connect our board to a panel right now.

  • 0 in reply to haitaka kanamura
    TI__Guru**** 189551 points

    Hi, 

    I don't see an issue with the schematic itself. Can you please dump out the entire DSI86 registers?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hi David,

    I changed my code to make it similar to the output of SN65DSI86_PANEL_VIDEOREGISTER_CALC. I also tested with semi-auto link training and normal mode. After that I dumped the register content of the IC. You can find the content in the attachment. I also attached my video register settings.

    Here is my new code:

        //======ASSR RW control  ======
        ret &= regmap_write(pdata->regmap, 0xFF, 0x7);
        ret &= regmap_write(pdata->regmap, 0x16, 0x1);
        ret &= regmap_write(pdata->regmap, 0xFF, 0x0);

        //======REFCLK Frequency  ======
        ret &= regmap_write(pdata->regmap, 0x0A, 0x6);

        //======DSI Mode  ======
        ret &= regmap_write(pdata->regmap, 0x10, 0x26);

        //======DSIA Clock  ======
        ret &= regmap_write(pdata->regmap, 0x12, 0x59);

        //======DSIB Clock  ======
        ret &= regmap_write(pdata->regmap, 0x13, 0x59);

        //======DP Datarate  ======
        ret &= regmap_write(pdata->regmap, 0x94, 0x80);

        //======Enable PLL  ======
        ret &= regmap_write(pdata->regmap, 0x0D, 0x1);

        //======Enable enhanced frame  in DSI86  ======
        ret &= regmap_write(pdata->regmap, 0x5A, 0x4);

        //======Number of DP lanes  ======
        ret &= regmap_write(pdata->regmap, 0x93, 0x20);

        //======Start Semi-Auto Link Training  ======
        ret &= regmap_write(pdata->regmap, 0x96, 0x01);

        //======CHA Active Line Length  ======
        ret &= regmap_write(pdata->regmap, 0x20, 0x80);
        ret &= regmap_write(pdata->regmap, 0x21, 0x07);

        //======CHB Active Line Length  ======
        ret &= regmap_write(pdata->regmap, 0x22, 0x0);
        ret &= regmap_write(pdata->regmap, 0x23, 0x0);

        //======Vertical Active Size   ======
        ret &= regmap_write(pdata->regmap, 0x24, 0x38);
        ret &= regmap_write(pdata->regmap, 0x25, 0x04);

        //======Horizontal Pulse Width   ======
        ret &= regmap_write(pdata->regmap, 0x2C, 0x2C);
        ret &= regmap_write(pdata->regmap, 0x2D, 0x00);

        //======Vertical Pulse Width   ======
        ret &= regmap_write(pdata->regmap, 0x30, 0x05);
        ret &= regmap_write(pdata->regmap, 0x31, 0x00);

        //======HBP   ======
        ret &= regmap_write(pdata->regmap, 0x34, 0x94);

        //======VBP   ======
        ret &= regmap_write(pdata->regmap, 0x36, 0x24);

        //===== HFP  ======
        ret &= regmap_write(pdata->regmap, 0x38, 0x58);

        //===== VFP  ======
        ret &= regmap_write(pdata->regmap, 0x3A, 0x04);

        //===== DP-18BPP Disable  ======
        ret &= regmap_write(pdata->regmap, 0x5B, 0x0);

        //===== Color Bar Enable  ======
        ret &= regmap_write(pdata->regmap, 0x3C, 0x17);

        //===== Enhanced Frame, and Vstream Enable  ======
        ret &= regmap_write(pdata->regmap, 0x5A, 0x0C);

    Fullscreen semi_training.txt Download 
    [   66.619006] ti_sn65: 09: 00
[   66.622308] ti_sn65: 0a: 86
[   66.625650] ti_sn65: 0b: 00
[   66.629769] ti_sn65: 0c: 00
[   66.633084] ti_sn65: 0d: 01
[   66.636410] ti_sn65: 0e: 00
[   66.639733] ti_sn65: 0f: 00
[   66.643027] ti_sn65: 10: 26
[   66.646317] ti_sn65: 11: 00
[   66.649657] ti_sn65: 12: 59
[   66.652975] ti_sn65: 13: 59
[   66.656311] ti_sn65: 14: 00
[   66.659646] ti_sn65: 15: 00
[   66.662927] ti_sn65: 16: 00
[   66.666240] ti_sn65: 17: 00
[   66.669561] ti_sn65: 18: 00
[   66.672872] ti_sn65: 19: 00
[   66.676195] ti_sn65: 1a: 00
[   66.679504] ti_sn65: 1b: 00
[   66.682794] ti_sn65: 1c: 00
[   66.686106] ti_sn65: 1d: 00
[   66.689418] ti_sn65: 1e: 00
[   66.692741] ti_sn65: 1f: 00
[   66.696060] ti_sn65: 20: 80
[   66.699356] ti_sn65: 21: 07
[   66.702643] ti_sn65: 22: 00
[   66.705953] ti_sn65: 23: 00
[   66.709279] ti_sn65: 24: 38
[   66.712591] ti_sn65: 25: 04
[   66.715912] ti_sn65: 26: 00
[   66.719200] ti_sn65: 27: 00
[   66.722480] ti_sn65: 28: 00
[   66.725811] ti_sn65: 29: 00
[   66.729124] ti_sn65: 2a: 00
[   66.732441] ti_sn65: 2b: 00
[   66.735760] ti_sn65: 2c: 2c
[   66.739056] ti_sn65: 2d: 00
[   66.742344] ti_sn65: 2e: 00
[   66.745650] ti_sn65: 2f: 00
[   66.748969] ti_sn65: 30: 05
[   66.752286] ti_sn65: 31: 00
[   66.755608] ti_sn65: 32: 00
[   66.758895] ti_sn65: 33: 00
[   66.762201] ti_sn65: 34: 94
[   66.765510] ti_sn65: 35: 00
[   66.768830] ti_sn65: 36: 24
[   66.772147] ti_sn65: 37: 00
[   66.775466] ti_sn65: 38: 58
[   66.778750] ti_sn65: 39: 00
[   66.782084] ti_sn65: 3a: 04
[   66.785402] ti_sn65: 3b: 00
[   66.788720] ti_sn65: 3c: 17
[   66.792033] ti_sn65: 3d: 00
[   66.795324] ti_sn65: 3e: 00
[   66.798614] ti_sn65: 3f: 00
[   66.801921] ti_sn65: 40: 62
[   66.805235] ti_sn65: 41: 46
[   66.808555] ti_sn65: 42: 00
[   66.811870] ti_sn65: 43: 00
[   66.815153] ti_sn65: 44: 80
[   66.818442] ti_sn65: 45: 00
[   66.821746] ti_sn65: 46: 98
[   66.825053] ti_sn65: 47: 08
[   66.828376] ti_sn65: 48: 65
[   66.831687] ti_sn65: 49: 04
[   66.834993] ti_sn65: 4a: c0
[   66.838284] ti_sn65: 4b: 00
[   66.841602] ti_sn65: 4c: 29
[   66.844921] ti_sn65: 4d: 00
[   66.848240] ti_sn65: 4e: 2c
[   66.851556] ti_sn65: 4f: 00
[   66.854844] ti_sn65: 50: 05
[   66.858162] ti_sn65: 51: 00
[   66.861500] ti_sn65: 52: 80
[   66.864812] ti_sn65: 53: 07
[   66.868133] ti_sn65: 54: 38
[   66.871450] ti_sn65: 55: 04
[   66.874741] ti_sn65: 56: 20
[   66.878043] ti_sn65: 57: 00
[   66.881347] ti_sn65: 58: 40
[   66.884672] ti_sn65: 59: e4
[   66.888001] ti_sn65: 5a: 0c
[   66.891294] ti_sn65: 5b: 00
[   66.894585] ti_sn65: 5c: 10
[   66.897893] ti_sn65: 5d: 00
[   66.901215] ti_sn65: 5e: 30
[   66.904538] ti_sn65: 5f: 00
[   66.907852] ti_sn65: 60: a0
[   66.911143] ti_sn65: 61: 60
[   66.914434] ti_sn65: 62: a4
[   66.917751] ti_sn65: 63: 00
[   66.921065] ti_sn65: 64: 00
[   66.924387] ti_sn65: 65: 00
[   66.927703] ti_sn65: 66: 00
[   66.931009] ti_sn65: 67: 00
[   66.934298] ti_sn65: 68: 00
[   66.937602] ti_sn65: 69: 00
[   66.940911] ti_sn65: 6a: 00
[   66.944221] ti_sn65: 6b: 00
[   66.947535] ti_sn65: 6c: 00
[   66.950822] ti_sn65: 6d: 00
[   66.954134] ti_sn65: 6e: 00
[   66.957467] ti_sn65: 6f: 00
[   66.960782] ti_sn65: 70: 00
[   66.964093] ti_sn65: 71: 00
[   66.967401] ti_sn65: 72: 00
[   66.970687] ti_sn65: 73: 00
[   66.973999] ti_sn65: 74: 00
[   66.977312] ti_sn65: 75: 01
[   66.980630] ti_sn65: 76: 02
[   66.983962] ti_sn65: 77: 00
[   66.987259] ti_sn65: 78: 80
[   66.990546] ti_sn65: 79: 00
[   66.993852] ti_sn65: 7a: 00
[   66.997168] ti_sn65: 7b: 00
[   67.000487] ti_sn65: 7c: 00
[   67.003807] ti_sn65: 7d: 00
[   67.007096] ti_sn65: 7e: 00
[   67.010376] ti_sn65: 7f: 00
[   67.013694] ti_sn65: 80: 00
[   67.017007] ti_sn65: 81: 00
[   67.020326] ti_sn65: 82: 00
[   67.023639] ti_sn65: 83: 00
[   67.026926] ti_sn65: 84: 00
[   67.030241] ti_sn65: 85: 00
[   67.033557] ti_sn65: 86: 00
[   67.036876] ti_sn65: 87: 00
[   67.040184] ti_sn65: 88: 00
[   67.043503] ti_sn65: 89: 1f
[   67.046787] ti_sn65: 8a: 7c
[   67.050120] ti_sn65: 8b: f0
[   67.053440] ti_sn65: 8c: c1
[   67.056760] ti_sn65: 8d: 07
[   67.060081] ti_sn65: 8e: 1f
[   67.063413] ti_sn65: 8f: 7c
[   67.066700] ti_sn65: 90: f0
[   67.070016] ti_sn65: 91: c1
[   67.073328] ti_sn65: 92: 07
[   67.076647] ti_sn65: 93: 20
[   67.079956] ti_sn65: 94: 80
[   67.083243] ti_sn65: 95: 00
[   67.086536] ti_sn65: 96: 00
[   67.089837] ti_sn65: 97: 04
[   67.093158] ti_sn65: 98: 01
[   67.096475] ti_sn65: 99: 00
[   67.099800] ti_sn65: a0: 01
[   67.103083] ti_sn65: a1: ff
[   67.106367] ti_sn65: a2: ff
[   67.109692] ti_sn65: a3: 00
[   67.113005] ti_sn65: a4: 00
[   67.116321] ti_sn65: a5: 00
[   67.119652] ti_sn65: b0: 04
[   67.122942] ti_sn65: b1: 78
[   67.126264] ti_sn65: b2: ac
[   67.129590] ti_sn65: b3: ac
[   67.132907] ti_sn65: b4: 08
[   67.136224] ti_sn65: b5: 6c
[   67.139542] ti_sn65: b6: 9c
[   67.142833] ti_sn65: b7: 9c
[   67.146139] ti_sn65: b8: 0c
[   67.149462] ti_sn65: b9: 5c
[   67.152781] ti_sn65: ba: 5c
[   67.156103] ti_sn65: bb: 5c
[   67.159411] ti_sn65: bc: 0c
[   67.162694] ti_sn65: bd: 0c
[   67.166030] ti_sn65: be: 0c
[   67.169348] ti_sn65: bf: 0c
[   67.172669] ti_sn65: c0: 3f
[   67.175985] ti_sn65: c1: 3f
[   67.179276] ti_sn65: c2: 0f
[   67.182565] ti_sn65: c3: 00
[   67.185872] ti_sn65: c8: 00
[   67.189188] ti_sn65: e0: 00
[   67.192514] ti_sn65: e1: 00
[   67.195824] ti_sn65: e2: 00
[   67.199119] ti_sn65: e3: 00
[   67.202407] ti_sn65: e4: 00
[   67.205713] ti_sn65: e5: 00
[   67.209029] ti_sn65: e6: 00
[   67.212345] ti_sn65: e7: 00
[   67.215655] ti_sn65: e8: 00
[   67.218942] ti_sn65: e9: 00
[   67.222281] ti_sn65: f0: 00
[   67.225596] ti_sn65: f1: 2b
[   67.228913] ti_sn65: f2: 00
[   67.232222] ti_sn65: f3: 00
[   67.235533] ti_sn65: f4: 08
[   67.238817] ti_sn65: f5: 02
[   67.242125] ti_sn65: f6: 00
[   67.245462] ti_sn65: f7: 00
[   67.248772] ti_sn65: f8: 02

    Fullscreen no training.txt Download 
    [   47.411627] ti_sn65: 09: 00
[   47.414922] ti_sn65: 0a: 86
[   47.418270] ti_sn65: 0b: 00
[   47.422390] ti_sn65: 0c: 00
[   47.425708] ti_sn65: 0d: 01
[   47.429025] ti_sn65: 0e: 00
[   47.432347] ti_sn65: 0f: 00
[   47.435636] ti_sn65: 10: 26
[   47.438929] ti_sn65: 11: 00
[   47.442272] ti_sn65: 12: 59
[   47.445596] ti_sn65: 13: 59
[   47.448918] ti_sn65: 14: 00
[   47.452241] ti_sn65: 15: 00
[   47.455530] ti_sn65: 16: 00
[   47.458824] ti_sn65: 17: 00
[   47.462138] ti_sn65: 18: 00
[   47.465461] ti_sn65: 19: 00
[   47.468786] ti_sn65: 1a: 00
[   47.472116] ti_sn65: 1b: 00
[   47.475407] ti_sn65: 1c: 00
[   47.478718] ti_sn65: 1d: 00
[   47.482041] ti_sn65: 1e: 00
[   47.485368] ti_sn65: 1f: 00
[   47.488688] ti_sn65: 20: 80
[   47.492009] ti_sn65: 21: 07
[   47.495298] ti_sn65: 22: 00
[   47.498618] ti_sn65: 23: 00
[   47.501934] ti_sn65: 24: 38
[   47.505260] ti_sn65: 25: 04
[   47.508577] ti_sn65: 26: 00
[   47.511903] ti_sn65: 27: 00
[   47.515191] ti_sn65: 28: 00
[   47.518525] ti_sn65: 29: 00
[   47.521845] ti_sn65: 2a: 00
[   47.525161] ti_sn65: 2b: 00
[   47.528486] ti_sn65: 2c: 2c
[   47.531785] ti_sn65: 2d: 00
[   47.535074] ti_sn65: 2e: 00
[   47.538395] ti_sn65: 2f: 00
[   47.541713] ti_sn65: 30: 05
[   47.545027] ti_sn65: 31: 00
[   47.548350] ti_sn65: 32: 00
[   47.551644] ti_sn65: 33: 00
[   47.554930] ti_sn65: 34: 94
[   47.558240] ti_sn65: 35: 00
[   47.561561] ti_sn65: 36: 24
[   47.564881] ti_sn65: 37: 00
[   47.568205] ti_sn65: 38: 58
[   47.571502] ti_sn65: 39: 00
[   47.574797] ti_sn65: 3a: 04
[   47.578106] ti_sn65: 3b: 00
[   47.581414] ti_sn65: 3c: 17
[   47.584740] ti_sn65: 3d: 00
[   47.588060] ti_sn65: 3e: 00
[   47.591343] ti_sn65: 3f: 00
[   47.594663] ti_sn65: 40: 66
[   47.598001] ti_sn65: 41: 46
[   47.601323] ti_sn65: 42: 00
[   47.604646] ti_sn65: 43: 00
[   47.607967] ti_sn65: 44: 80
[   47.611264] ti_sn65: 45: 00
[   47.614572] ti_sn65: 46: 98
[   47.617894] ti_sn65: 47: 08
[   47.621211] ti_sn65: 48: 65
[   47.624538] ti_sn65: 49: 04
[   47.627834] ti_sn65: 4a: c0
[   47.631118] ti_sn65: 4b: 00
[   47.634439] ti_sn65: 4c: 29
[   47.637763] ti_sn65: 4d: 00
[   47.641087] ti_sn65: 4e: 2c
[   47.644405] ti_sn65: 4f: 00
[   47.647701] ti_sn65: 50: 05
[   47.650992] ti_sn65: 51: 00
[   47.654329] ti_sn65: 52: 80
[   47.657648] ti_sn65: 53: 07
[   47.660964] ti_sn65: 54: 38
[   47.664282] ti_sn65: 55: 04
[   47.667578] ti_sn65: 56: 20
[   47.670866] ti_sn65: 57: 00
[   47.674195] ti_sn65: 58: 40
[   47.677514] ti_sn65: 59: e4
[   47.680843] ti_sn65: 5a: 0c
[   47.684159] ti_sn65: 5b: 00
[   47.687445] ti_sn65: 5c: 10
[   47.690788] ti_sn65: 5d: 00
[   47.694111] ti_sn65: 5e: 30
[   47.697429] ti_sn65: 5f: 00
[   47.700744] ti_sn65: 60: a0
[   47.704071] ti_sn65: 61: 60
[   47.707359] ti_sn65: 62: a4
[   47.710670] ti_sn65: 63: 00
[   47.714011] ti_sn65: 64: 00
[   47.717331] ti_sn65: 65: 00
[   47.720653] ti_sn65: 66: 00
[   47.723976] ti_sn65: 67: 00
[   47.727262] ti_sn65: 68: 00
[   47.730582] ti_sn65: 69: 00
[   47.733895] ti_sn65: 6a: 00
[   47.737225] ti_sn65: 6b: 00
[   47.740544] ti_sn65: 6c: 00
[   47.743837] ti_sn65: 6d: 00
[   47.747127] ti_sn65: 6e: 00
[   47.750442] ti_sn65: 6f: 00
[   47.753753] ti_sn65: 70: 00
[   47.757094] ti_sn65: 71: 00
[   47.760416] ti_sn65: 72: 00
[   47.763712] ti_sn65: 73: 00
[   47.767004] ti_sn65: 74: 00
[   47.770311] ti_sn65: 75: 00
[   47.773615] ti_sn65: 76: 00
[   47.776935] ti_sn65: 77: 00
[   47.780269] ti_sn65: 78: 00
[   47.783561] ti_sn65: 79: 00
[   47.786853] ti_sn65: 7a: 00
[   47.790178] ti_sn65: 7b: 00
[   47.793504] ti_sn65: 7c: 00
[   47.796821] ti_sn65: 7d: 00
[   47.800140] ti_sn65: 7e: 00
[   47.803431] ti_sn65: 7f: 00
[   47.806743] ti_sn65: 80: 00
[   47.810065] ti_sn65: 81: 00
[   47.813388] ti_sn65: 82: 00
[   47.816705] ti_sn65: 83: 00
[   47.820023] ti_sn65: 84: 00
[   47.823310] ti_sn65: 85: 00
[   47.826626] ti_sn65: 86: 00
[   47.829950] ti_sn65: 87: 00
[   47.833265] ti_sn65: 88: 00
[   47.836604] ti_sn65: 89: 1f
[   47.839929] ti_sn65: 8a: 7c
[   47.843216] ti_sn65: 8b: f0
[   47.846532] ti_sn65: 8c: c1
[   47.849850] ti_sn65: 8d: 07
[   47.853166] ti_sn65: 8e: 1f
[   47.856487] ti_sn65: 8f: 7c
[   47.859784] ti_sn65: 90: f0
[   47.863080] ti_sn65: 91: c1
[   47.866405] ti_sn65: 92: 07
[   47.869727] ti_sn65: 93: 20
[   47.873045] ti_sn65: 94: 80
[   47.876363] ti_sn65: 95: 00
[   47.879654] ti_sn65: 96: 01
[   47.882949] ti_sn65: 97: 04
[   47.886251] ti_sn65: 98: 01
[   47.889563] ti_sn65: 99: 00
[   47.892883] ti_sn65: a0: 01
[   47.896204] ti_sn65: a1: ff
[   47.899503] ti_sn65: a2: ff
[   47.902794] ti_sn65: a3: 00
[   47.906133] ti_sn65: a4: 00
[   47.909455] ti_sn65: a5: 00
[   47.912772] ti_sn65: b0: 04
[   47.916092] ti_sn65: b1: 78
[   47.919377] ti_sn65: b2: ac
[   47.922694] ti_sn65: b3: ac
[   47.926016] ti_sn65: b4: 08
[   47.929334] ti_sn65: b5: 6c
[   47.932649] ti_sn65: b6: 9c
[   47.935967] ti_sn65: b7: 9c
[   47.939262] ti_sn65: b8: 0c
[   47.942569] ti_sn65: b9: 5c
[   47.945888] ti_sn65: ba: 5c
[   47.949212] ti_sn65: bb: 5c
[   47.952528] ti_sn65: bc: 0c
[   47.955825] ti_sn65: bd: 0c
[   47.959115] ti_sn65: be: 0c
[   47.962450] ti_sn65: bf: 0c
[   47.965770] ti_sn65: c0: 3f
[   47.969098] ti_sn65: c1: 3f
[   47.972413] ti_sn65: c2: 0f
[   47.975708] ti_sn65: c3: 00
[   47.978998] ti_sn65: c8: 00
[   47.982313] ti_sn65: e0: 00
[   47.985634] ti_sn65: e1: 00
[   47.988955] ti_sn65: e2: 00
[   47.992276] ti_sn65: e3: 00
[   47.995572] ti_sn65: e4: 00
[   47.998872] ti_sn65: e5: 00
[   48.002175] ti_sn65: e6: 00
[   48.005488] ti_sn65: e7: 00
[   48.008809] ti_sn65: e8: 00
[   48.012125] ti_sn65: e9: 00
[   48.015412] ti_sn65: f0: 00
[   48.018729] ti_sn65: f1: 2b
[   48.022070] ti_sn65: f2: 00
[   48.025389] ti_sn65: f3: 00
[   48.028707] ti_sn65: f4: 00
[   48.032026] ti_sn65: f5: 02
[   48.035315] ti_sn65: f6: 00
[   48.038626] ti_sn65: f7: 00
[   48.041949] ti_sn65: f8: 00

    4380.SN65DSI86_PANEL_VIDEOREGISTER_CALC.zip

  • 0 in reply to haitaka kanamura
    TI__Guru**** 189551 points

    Hi,

    Can you please connect the panel? The register dump shows link training failure. If training is unsuccessful, the DSIx6 will transition the ML_TX_MODE to Main Link Off.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hi David,

    We disconnected the sn65dsi86 from tusb546 and connected it to a monitor through dp port. We connected 2 dp lanes and aux lane to the monitor. This didn't work either. Link training still fails. I tweaked registers from 0xB0 to 0xBF and from 0xC0 to 0xC3. This didn't help either. The status registers indicate that there are some problems with DSI-A channel; however I think that link failure problem is not caused by the DSI problems.

    Do you have any other suggestions? Here is my register dump:

    [   34.803375] ti_sn65: f0: 00
    [   34.806690] ti_sn65: f1: 2b
    [   34.810030] ti_sn65: f2: 00
    [   34.814161] ti_sn65: f3: 00
    [   34.817497] ti_sn65: f4: 00
    [   34.820823] ti_sn65: f5: 02
    [   34.824116] ti_sn65: f6: 00
    [   34.827421] ti_sn65: f7: 00
    [   34.830747] ti_sn65: f8: 12

    Thanks for your help.

  • 0 in reply to haitaka kanamura
    TI__Guru**** 189551 points

    Hi,

    If the color bar is enabled, we can ignore the DSI error for now since the DSI86 internally generates the color bar. But the register 0xF8 shows link training failure and failure is associated with the EQ training phase of the link training. I would expect if you increase the pre-emphasis for each level, you may able to get the link training to pass. Do you have a way to monitor and capture the link training between the DSI86 and the monitor?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hi David,

    I tried to capture the link training data; but during link training there is no output on dp lanes. However we can see data on aux lanes. I don't know why there is no data on dp lanes during link training. I expect that if there is data on aux lanes, then there should be data on dp lanes as well.

  • 0 in reply to haitaka kanamura
    Prodigy 70 points

    Hi David,

    I also tried 80 bit custom pattern test. I guess only setting 0x08 to register 0x96 is enough to activate this test after adjusting lane counts and data rate. But even in this condition I see no data on dp lanes.

  • 0 in reply to haitaka kanamura
    TI__Guru**** 189551 points

    Hi,

    Does the panel support 2 lane or 4 lane DP mode? I attached two script files, one is 2 DP lane color bar and second is 4 DP lane color bar, can you please see if either one of them work when connecting the panel directly to the DSI86 output?

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/2DP_5F00_4DSI_5F00_RBR_5F00_800x600_5F00_Color_5F00_Bar.7z

    Fullscreen 4DP_4DSI_RBR_800x600_Color_Bar.xml Download 
    <aardvark>
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
    <i2c_bitrate khz="100"/>
    
  <i2c_write addr="0x2D" count="1" radix="16">5C 01</i2c_write> <sleep ms="10"/>

   <i2c_write addr="0x2D" count="1" radix="16">FF 07</i2c_write> <sleep ms="10"/>

======DUMP CFR======
   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>


   <i2c_write addr="0x2D" count="1" radix="16">16 01</i2c_write> <sleep ms="10"/>

   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>

  <i2c_write addr="0x2D" count="1" radix="16">FF 00</i2c_write> <sleep ms="10"/>


======Single 4 DSI lanes======

  <i2c_write addr="0x2D" count="1" radix="16">10 26 </i2c_write> <sleep ms="10"/>

======DSI CLK FREQ======

  <i2c_write addr="0x2D" count="0" radix="16">12 </i2c_write> <sleep ms="10"/>
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>



======enhanced framing======

  <i2c_write addr="0x2D" count="1" radix="16">5A 04 </i2c_write> <sleep ms="10"/>


======ADDR 0x93 CFR======

   <i2c_write addr="0x2D" count="0" radix="16">93</i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="6" radix="16">00</i2c_read> <sleep ms="10"/>

======Pre0dB 1 lanes no SSC======
   <i2c_write addr="0x2D" count="1" radix="16">93 30</i2c_write> <sleep ms="10"/>

======L0mV RBR======
   <i2c_write addr="0x2D" count="1" radix="16">94 20</i2c_write> <sleep ms="10"/>

======POST2 0dB ======
   <i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> <sleep ms="10"/>

======PLL ENABLE======
   <i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10"/>
   <i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> <sleep ms="10"/>
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>



======Semi-Auto TRAIN ======
   <i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20"/>


======ADDR 0x0A CFR======

   <i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> <sleep ms="20"/>

======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>

=====CHA_ACTIVE_LINE_LENGTH=======
    <i2c_write addr="0x2D" count="2" radix="16">20 00 04</i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_DISPLAY_SIZE=======
    <i2c_write addr="0x2D" count="2" radix="16">24 58 02</i2c_write> <sleep ms="10"/>

=====CHA_SYNC_DELAY=======
    <i2c_write addr="0x2D" count="2" radix="16">28 00 00</i2c_write> <sleep ms="10"/>

=====CHA_HSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">2C 80 80</i2c_write> <sleep ms="10"/>

=====CHA_VSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">30 04 80</i2c_write> <sleep ms="10"/>

=====CHA_HORIZONTAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">34 28 </i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">36 09</i2c_write> <sleep ms="10"/>

=====CHA_HORIZONTAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">38 28</i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">3A 01</i2c_write> <sleep ms="10"/>

=====DP_18BPP_EN =======
  <i2c_write addr="0x2D" count="1" radix="16">5B 01 </i2c_write> <sleep ms="100"/>

=====COLOR BAR =======
    <i2c_write addr="0x2D" count="1" radix="16">3C 10</i2c_write> <sleep ms="100"/>

======enhanced framing and Vstream enable======

  <i2c_write addr="0x2D" count="1" radix="16">5A 0C </i2c_write> <sleep ms="100"/>

======DUMP CFR======
    <i2c_write addr="0x2D" count="0" radix="16">20</i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="32" radix="16">00</i2c_read> <sleep ms="10"/>



</aardvark>

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hi David,

    Panel supports 2 lanes. Our panel has nxp's ptn3460 IC. We connect the sn65dsi86's pins directly to its pins. In case where I tried 80bit custom pattern test, shouldn't I see anything on the lanes even if there is no panel connection? I thought when 80 bit custom pattern test is activated, there should have been some signal pattern on the lanes.

    I tried 2DP color pattern script that you sent and I do not see anything on the panel or the lanes either. Here is register dump:

    [   20.297185] ti_sn65 0x16: 00
    [   20.325172] ti_sn65 0x16: 01
    [   20.365578] ti_sn65 0x12: 55 00
    [   20.393622] ti_sn65: 0x93: 04 04 00 00 c8 00
    [   20.461259] ti_sn65 0x0A: 84 04
    [   20.501172] ti_sn65 0x96: 00
    [   20.923938] ti_sn65 20: 00
    [   20.926749] ti_sn65 21: 58
    [   20.929570] ti_sn65 22: 00
    [   20.932363] ti_sn65 23: 80
    [   20.940760] ti_sn65 24: 04
    [   20.943553] ti_sn65 25: 28
    [   20.946389] ti_sn65 26: 28
    [   20.949212] ti_sn65 27: 10
    [   20.952007] ti_sn65 28: 40
    [   20.954834] ti_sn65 29: 00
    [   20.957654] ti_sn65 2a: 40
    [   20.960450] ti_sn65 2b: 00
    [   20.968761] ti_sn65 2c: 00
    [   20.971553] ti_sn65 2d: 00
    [   20.974370] ti_sn65 2e: c8
    [   20.977192] ti_sn65 2f: 00
    [   20.979990] ti_sn65 30: 00
    [   20.982801] ti_sn65 31: fc
    [   20.985629] ti_sn65 32: 90
    [   20.988426] ti_sn65 33: 00
    [   20.996760] ti_sn65 34: 2d
    [   20.999554] ti_sn65 35: 00
    [   21.002403] ti_sn65 36: 00
    [   21.005235] ti_sn65 37: 00
    [   21.008031] ti_sn65 38: 60
    [   21.010844] ti_sn65 39: 00
    [   21.013664] ti_sn65 3a: 00
    [   21.016458] ti_sn65 3b: 00
    [   21.024760] ti_sn65 3c: 01
    [   21.027552] ti_sn65 3d: 00
    [   21.030373] ti_sn65 3e: 02
    [   21.033199] ti_sn65 3f: 00

  • 0 in reply to haitaka kanamura
    TI__Guru**** 189551 points

    Hi,

    It looks like the DSI86 registers are not being set correctly or being overwritten.

    For example, in the script example I sent

    =====CHA_VERTICAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">36 09</i2c_write> <sleep ms="10"/>

    =====CHA_HORIZONTAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">38 28</i2c_write> <sleep ms="10"/>

    =====CHA_VERTICAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">3A 01</i2c_write> <sleep ms="10"/>

    =====DP_18BPP_EN =======
    <i2c_write addr="0x2D" count="1" radix="16">5B 01 </i2c_write> <sleep ms="100"/>

    =====COLOR BAR =======
    <i2c_write addr="0x2D" count="1" radix="16">3C 10</i2c_write> <sleep ms="100"/>

    Color bar is being enabled and set to vertical color.

    But the register dump shows register 0x3C to be 0x01, which means the color bar is disabled. Can you double check the I2C interface?

    Thanks

    David