SN65DSI84: Is it possible to check the LVDS test pattern even if the 0xe5 value is 1?

user6481366

Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hi,

After making the SN65DSI84 device driver for Linux, I made the initial code through DSI-Tuner.

When I check 0xE5, the result is 1 instead of 0.

Looking at several q&a, it is called a CLK problem, but according to the document below, it is stated that DSI Data is not required when creating an LVDS Test Pattern.

I want to check LVDS test pattern without DSI input.

Is it possible to check the LVDS test pattern even if the 0xe5 value is 1?

Any answers would be appreciated.

Thanks

Choi.

over 4 years ago

0 Ikechukwu Anyiam over 4 years ago

TI__Mastermind 35130 points

Hi Choi,

A clock is still needed for the test pattern (either the DSI CLK or an external REF CLK).

Also, make sure you're enabling the PLL (register 0x0D) as the DSI-Tuner won't enable it for you.

Regards,

I.K.

0 user6481366 over 4 years ago in reply to Ikechukwu Anyiam

Prodigy 80 points

Hi, I.K.

Thanks for your quick response.

I've rechecked DSI CLK and I modified register values using DSI Tuner.

Could you please check our register setting?

this is our LVDS panel info.

clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
hfront-porch = <88>;
hsync-len = <44>;
hback-porch = <148>;
vfront-porch = <4>;
vsync-len = <5>;
vback-porch = <36>;
vsync-active = <5>;
hsync-active = <44>;

and below is our setting for DSI tuner.

our DSI Ch A CLK result is like below.

(LVDS CLKS(148.5) * BPP(24) * 2) / (4 * 2) = 891 mhz.

divisor is 6.

Finally, I added registers to device tree then the result of 0xE5 register was 0x1 after PLL_EN is enabled.

sn65dsi84,addresses = <

0x09 0x0A 0x0B 0x0D

0x10 0x11 0x12 0x13

0x18 0x19 0x1A 0x1B

0x20 0x21 0x22 0x23

0x24 0x25 0x26 0x27

0x28 0x29 0x2A 0x2B

0x2C 0x2D 0x2E 0x2F

0x30 0x31 0x32 0x33

0x34 0x35 0x36 0x37

0x38 0x39 0x3A 0x3B

0x3C 0x3D 0x3E 0x0D>;

sn65dsi84,values = <

0x00 0x0b 0x28 0x00

0x26 0x00 0xb2 0x00

0x6f 0x00 0x03 0x00

0xc0 0x03 0x00 0x00

0x38 0x04 0x00 0x00

0x20 0x00 0x00 0x00

0x2c 0x00 0x00 0x00

0x05 0x00 0x00 0x00

0x94 0x00 0x24 0x00

0x58 0x00 0x04 0x00

0x00 0x00 0x00 0x00>;

Our DSI MIPI setting is below.

qcom,mdss-dsi-panel-type = "dsi_video_mode";

qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;

qcom,mdss-dsi-virtual-channel-id = <0>;

qcom,mdss-dsi-stream = <0>;

qcom,mdss-dsi-bpp = <24>;

qcom,mdss-dsi-underflow-color = <0xff>;

qcom,mdss-dsi-border-color = <0>;

qcom,mdss-dsi-traffic-mode = "burst_mode";

qcom,mdss-dsi-force-clock-lane-hs;

qcom,mdss-dsi-bllp-power-mode;

qcom,mdss-dsi-bllp-eof-power-mode;

qcom,mdss-dsi-panel-clockrate = <891000000>;

qcom,mdss-dsi-reset-sequence = <1 10>;

qcom,mdss-dsi-lane-0-state;

qcom,mdss-dsi-lane-1-state;

qcom,mdss-dsi-lane-2-state;

qcom,mdss-dsi-lane-3-state;

qcom,mdss-dsi-dma-trigger = "trigger_sw";

qcom,mdss-dsi-mdp-trigger = "none";

qcom,mdss-dsi-lane-map = "lane_map_0123";

qcom,mdss-dsi-panel-timings = [00 1E 08 07 24 22 08 08 08 02 04 00];

qcom,mdss-dsi-t-clk-post = <0x0D>;

qcom,mdss-dsi-t-clk-pre = <0x32>;

qcom,mdss-dsi-h-sync-pulse =<1>;

qcom,mdss-dsi-display-timings {

timing@0{*/

qcom,mdss-dsi-panel-width = <1920>;

qcom,mdss-dsi-panel-height = <1080>;

qcom,mdss-dsi-h-front-porch = <88>;

qcom,mdss-dsi-h-back-porch = <148>;

qcom,mdss-dsi-h-pulse-width = <44>;

qcom,mdss-dsi-h-sync-skew = <0>;

qcom,mdss-dsi-v-back-porch = <36>;

qcom,mdss-dsi-v-front-porch = <4>;

qcom,mdss-dsi-v-pulse-width = <5>;

qcom,mdss-dsi-panel-framerate = <60>;

qcom,mdss-dsi-on-command = [

05 01 00 00 64 00 02 11 00

05 01 00 00 14 00 02 29 00];

qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00

05 01 00 00 78 00 02 10 00];

qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

qcom,display-topology = <1 0 1>;

qcom,default-topology-index = <0>;

};

Could you analyze our setting issue?

Thanks

Choi

0 user6481366 over 4 years ago in reply to Ikechukwu Anyiam

Prodigy 80 points

Oh my god.

I just changed sugested DSI CLK, then it works!

Thanks :)

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SN65DSI84: Is it possible to check the LVDS test pattern even if the 0xe5 value is 1?