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Original question:

SN65DSI86: External Displays

SN65DSI86-Q1: Driving a display port connector instead of eDP

WST
Expert 1015 points
Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: TEST2,

In section 9.1 of the datasheet it says the following:

"The SN65DSIx6 is a bridge which interfaces DSI to embedded DisplayPort (eDP). Because it does not support HDCP, it is only intended for internal applications like notebooks and tablets. Four lanes of HBR2 (17.28 Gbps before 8b10b encoding) and dual DSI input (up to 8 lanes at 1.5 Gbps for a total of 12 Gbps) allows the SN65DSIx6 to support large high resolution eDP panels."

I want to drive a DP connector and I don't need the HDCP, so is this ok? Can I drive a connector directly?

Do I have to do something with the TEST inputs to make this work?

  • 0
    TI__Guru**** 177476 points

    Hi,

    You can drive the DP connector directly with the DSI86.

    Since most DP monitors do not support ASSR, it is importance to have the TEST2 pin pulled high to enable the read/write control of the DSI86 ASSR. The ASSR is enabled by default, but with the TEST2 pin pulled high, the ASSR can then be disabled through the DSI86 I2C register.

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    Expert 1015 points

    Thank you for the QUICK answer!!

    The datasheet says this about TEST2:

    TEST2 55 I/O PD     Used for internal test, HBR2 Compliance Eye, and Symbol Error Rate Measurement pattern. For normal operation, this pin should be pull-down to ground or left unconnected. Refer to DP Training and Compliance patterns for information on HBR2 Compliance Eye and Symbol Error Rate Measurement patterns

    It doesn't mention the ASSR operation related to this pin.

    When you say 'pulled high' is that to 1.8V?

    I don't know a lot about DisplayPort, but it sounds like you are saying then this pin needs to be pulled high and then the I2C interface is used to program the register 0x5A to set the 2 LSBs to 00?
    Can this pin be left high? It says for 'normal operation' it should be pulled low. Is there something else that needs to be done after programming the above register to make sure that tests aren't run?

  • 0 in reply to WST
    TI__Guru**** 177476 points

    Hi,

    ASSR needs to be turned off in order to run the DP compliance testing. So pulling TEST2 pin high is for both DP compliance testing and to disable ASSR.

    To disable ASSR, pull TEST2 pin high to 1.8V VCCIO

    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    TEST2 pin can be left high.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Expert 1015 points

    OK. As long as this is an approved method of operation then that is fine with me. It is odd that it takes both TEST2 = high and register 0x16 to be set, especially since that seems to be the purpose of register 0x16 in page7.

    Thanks for the step-by-step description.

    Also, the latest sn65dsi86-Q1 datasheet has an error in Table 32. Page Select Register. It doesn't show the address of 0xFF or the bits of [2:0]. I thought at first that maybe the above steps didn't apply to the -Q1 version of the part, but it looks like the .pdf is just blank. I submitted feedback on the documentation.

    I'm assuming that the Q1 works like the standard BGA part and the register map is the same.

  • 0 in reply to WST
    TI__Guru**** 177476 points

    Hi,

    Your understanding is correct, the register map is the same between the Q1 and non-Q1 device.

    Thanks

    David