TPD3E001: ESD Application for ADS1292/1298 = not expected High-Resistant 0 to 3V3 Error 0,8V-DC ?? with ESD diode TPD3E001DRLR

Hello Andreas,

Thanks for using E2E! I'm having difficulty understanding your problem. Are you saying that the line TPD3E001 is protecting is going from 1.65 V to 0.8 V? 

Also, could you provide a clearer schematic of your system? It's difficult to understand what's going on based on the drawing, but it looks like TPD3E001's IO pin is just connected to a capacitor in parallel and the Vcc pin is connected to a 3.3 V supply. What lines are you trying to protect? 

Regards,

Matt Smith

Hello Matt,  

see below principle circuit diagramm of input ADS1292/1292 Input interface with ESD protection

Best regards Andreas

ADS1292-1298 ESD Myo-Input TPD3E001DRLRG4.pdf

Hello Matt,

your question:  YES, the line TPD3E001 is protecting is going from 1.65 V-DC  to 0.8 V-DC ?

                         You remove diode protecting IC and you have right calculated  1.65V-DC on middle Input points of 4M7-4M7.

                          See schematic snapshot on Top entry.

We do are not understand these effects and believe we get trouble with different OP input (+) to (-) include DC-offset

in due to of different diode middle voltage. Die diode has an clamp/break voltage > 25V and current <1nA, see datasheet.

Best regards Andreas

Hello Andreas,

I'm assuming the J1 blocks are the connectors. I would try disconnecting your Vcc pin on the TPD3E001 and see if that improves anything. Using the same supply for your pull up and Vcc might be causing the signal line to conduct through the forward diode and leak into the 3.3 V supply. Here is another E2E post with a similar issue/solution. 

Let me know if this works.

Regards,

Matt

Hello Matt,

please send me in your reference Ticket below the  "slyt561.pdf"  app note. 

The voltage divider level R_4M7 to R_4M7  on middle point +1,67V-DC will be strong loaded to GND via diode not by diode to 3V3.

The quite DC-level has been reduced to +0,8V-DC without any input signal. The AC signal level is approx.  max to +/- 300yV... 300mV

I hope, your "slyt561.pdf" include an science explanation of these effects. Otherwise such clumping diodes did are generally not usable ?? 

=========== your reference Ticket Request LINK  ===================

https://e2e.ti.com/support/interface/f/138/p/684636/2525132?tisearch=e2e-sitesearch&keymatch=TPD3E001%20pullup#2525132

My recommendation would be not connect VCC pin or use a different part that doesn't have a VCC pin.

We have an app note explaining why VCC is not needed in our newer parts  www.ti.com/.../slyt561.pdf

=============================

sorry Matt, I forget an best regards to you. We are very interested to your solution appl. note "slyt561.pdf.

Thanks in advance and best regards Andreas from Germany

Hello Andreas,

Here's the fixed link to that app note. The content about Vcc pins is on page 23. 

I have a few more possible scenarios and follow up questions that might explain your problem:

1. Is this error happening on one specific chip, or does it happen on all chips? I would suggest swapping a chip out for another one to see if you experience the same effect.
2. Have you confirmed that the chip orientation is correct? If the chipped is flipped around, the signal could be going through a forward conducting diode causing the 0.8 V drop. 
3. I would setup an ammeter to check the leakage current from the Vcc and GND pins in the device. There is only supposed to be 1 nA of leakage current. 
4. Is the ADS1292 powered on or off when you are conducting your tests? If it is powered off, one of its internal protection diodes could be forward conducting and causing leakage through its Vcc pin.

Please let me know if you need me to clarify anything.

Regards,

Matt 

Hi Matt

to 1). YES, same results on every 10 boards in 2 different Board-designs, see on top circuit diagram snapshot

to 2) YES,  the diode array TPD3E001 has an asymmetrical case with 5pins, not able to mismatch IC orientation

to 3) The design is to small to modify and measure. But at other design with de-coupled ESD-diode I measure:

          +0,8V-DC on middle point of  3V3 > R3_4.7Mohm > +0.8V-DC (MiddlePoint) > +R2_4.7Mohm > GND.  

           Attention:  from +0,8V-DC MiddlePoint (expected calculated +1,65V-DC) to  ADS1292 Pin-4 INP1P via

           R1_10K  measure by Oscilloscope  +0,8V-DC.   Reason: ADS1292 In1P/N Pin-4+3)to In2P/N (Pin6+5)

           short circuit to +0,8V-DC in power mode working condition.

           Sorry, I revise my 1st statement: "without diode rise up +0,8V-DC to +1,47V-DC.  A 2nd measure show

           the same result +0,8V-DC.  Reason  analogue input of ADS1292 has an DC input impedance of < 1Mohm

           in operation power mode 3V3. 

 to 4)  YES, ADS1292/1298 are powered by 3V3.   As result ref. to 3)  that means = Reason & Result:

            - ADS1292 In1P/N Pin-4+3)to In2P/N (Pin6+5) short circuit to +0,8V-DC in power mode working condition.

            - The problem is not  ESD-diodes TPD3E001, the really effects +0,8V-DC is a result of ADS1292 / ADS1298

               DC amplifier load impedance to internal  AGND-Ground of ADS1292 / ADS1298 !!

---------------------

Matt:        Did you conform:

a)  The ADS1292 and ADS1298 has an internal low resistance DC-input load in operation power mode 

     approximately of  < 1Mohm.  This could be the explanation. In these case we have an parallel condition of:

     +0,8V-DC on middle point of  3V3 > R3_4.7Mohm > +0.8V-DC (MiddlePoint) > +R2_4.7Mohm // 1Mohm ADC129x > GND

     These should be in opposite to the ADS129x application note with an 10Mohm/10Mohm voltage divider. We use only 2x 4M7ohm.

      --> A asynchrony voltage divider with  3V3 > R3_1Mohm >  +1,48V > R2_4,7Mohm //1Mohm ADC129x -> GND

b) Referred datasheet ADS1292 (chapter 6.2. ESD Ratings) & ADS1298 (chapter 7.2 ESD Ratings) should be an internal

    IC analog ESD protection  = OK  without  diodes TPD3E001 ??

c) See attachment:   - ADS1292 Analoge Input characteristics chapter 6.5.jpg 

                                 - ADS1292 Input Differential Dynamic Rane 8-3-4-2.jpg

d) Conclusion:   see our "old" Interface design 1st with static overvoltage DC-load effects on ADS129x inputs

     and "new" interface without static overvoltage DC-load effects appropriate to application note of ADS129x.

    - ESD old Interface Symetrical-Inputs (with static overload error).pdf

    - ESD new Interface voltage-devider (no static overload).pdf

    What is your recomendation for the right interface application for our ADS129x  input EMG inputs with ESD protection??

    I think, we have only a chance to start and realise the "new" interface design and test it ??

Best regard Andreas   6.11.2020 / 10:51 local time , Germany

ADS1292 Analoge Input characteristics chapter 6.5.jpg

ADS1292 Input Differential Dynamic Rane 8-3-4-2,jpg

ESD old Interface Symetrical-Inputs (with static overload error).jpg

ESD new Interface voltage-devider (no static overload).jpg

Hi Andreas,

a.) Can you confirm that the low input impedance is causing the voltage drop across R3?

b.) I would still advise having external ESD protection diodes. The ADS internal diodes are only rated for HBM and CDM. This is mainly to protect against manufacturing and assembly ESD events, not end-use ESD events. Our external protection didoes are rated for IEC61000-4-2, which is a much more rigorous testing process. You can learn more about it here. 

d.) The ESD diodes should be placed as close to the external connectors as possible, preferably on the other side of the coupling capacitor. This is to reduce parasitic inductance. You can read more about it in this layout guide on page 3. Here is also a video about protecting ADCs. 

I cannot speak too much about the ADS1292 since it is not a product in my assigned portfolio. I only specialize in ESD devices. However, if I've answered all of your ESD related questions, I can reassign this post to the team responsible for the ADS1292, and they can answer any more questions you have about it. 

Regards,

Matt