DP83867E: Built In Self Test (BIST) Thread

Alden Chico

Part Number: DP83867E
Other Parts Discussed in Thread: USB-2-MDIO

Hello,

I work for a CM and a board we're working on uses the DP83867ERGZT Ethernet PHY IC. We need to test the functionality of this chip using the BIST described in the device's datasheet and would like to know if it's possible to complete the BIST entirely through the RJ45 JTAG interface without access to the MAC (which in this application is a Xilinx FPGA) or a clock signal provided to the chip's XI pin. Please let me know what you think.

- Alden

over 4 years ago

0 Nikhil Menon over 4 years ago

TI__Genius 11725 points

Hi Alden,

Yes, as described in section 8.4.5 of the datasheet. The BIST packet generator can be configured to send packets out across the MDI. Register 0x16 is used to enable the PRBS generator. Please let me know if you have any further questions.

Thank you,

Nikhil

0 Alden Chico over 4 years ago in reply to Nikhil Menon

Prodigy 20 points

Hi Nikhil,

Thanks for getting on this thread. I'd like to know two things:

1. Does the PHY allow me to access register 0x16 using only the JTAG interface?

2. Do I need to set the clock signal XI during the BIST?

Alden

0 Nikhil Menon over 4 years ago in reply to Alden Chico

TI__Genius 11725 points

Hi Alden,

1. Register's can be accessed through MDC/MDIO pins. As one option, you may use our USB-2-MDIO tool linked here:

2. PHY should always be supplied with a clock on XI.

Thank you,

Nikhil

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DP83867E: Built In Self Test (BIST) Thread