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CCS/SN65DPHY440SS: Dphy440 DB side problem

Part Number: SN65DPHY440SS

Tool/software: Code Composer Studio

Dear TI Support team

      When I use dphy440 as a repeater, I encounter the following problems: using 4lane mode (single lane mode is also tested, the phenomenon is consistent)

1,My test platform is normal. My PCB design is designed in strict accordance with the signal characteristic specification, and the corresponding impedance matching has been done. To ensure that the test platform has no problem, I first connect senro to my platform, test OK, and then connect it to dphy440 board. (one module for sensor, one module for dphy440 and one module for master control).

2, The sensor of Sony imx214 series can output signal and plot normally after adding dphy440. The input and output of signal measured by oscilloscope are normal;

3, The sensor of Sony imx314 series can not output the image. After measuring with oscilloscope, it is found that the four pairs of differential pair signals output from the sensor end to the input end of dphy440 chip are normal; however, the lane0 from dphy440 output end to main control chip has no HS signal, and the other three Lane signals are normal. Reduce the speed to very low (6mhz) phenomenon is the same;

4, I put cfg0, cfg1, erc, EQ have combined debugging, the problem is still the same.

5, After I cut off the dphy440 board to the main control chip, I found that the DB end of dphy440 has HS signal output;

6, Try some other sensors, some normal, some abnormal, abnormal phenomenon, such as Sony imx314.

  • Hi,

    The DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0.

    Try following for enabling lane0 HS path:

    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled.


    Bit 0 is lane 0

    Thanks

    David