DS90UB941AS-Q1: DS90UB941 + DS90UB948

Hi Hamzeh, Thanks I am following the document but couldn't see anything. My settings for UB941 is:

0x01, (1 << 0 | 1 << 1) // reset 
0x03, (1 << 3)  // enable pass thru
0x65, (0 << 4)  // 24bit
0x65, (1 << 2)  // own timings
0x65, (0 << 3)  // Internal clock source
0x66, 0x03      // video timings
0x67, 0x4 
0x66, 0x07
0x67, 0x80
0x66, 0x08
0x67, 0x07
0x66, 0x09
0x67, 0x2D
0x66, 0x04
0x67, 0x00
0x66, 0x05
0x67, 0x98
0x66, 0x06
0x67, 0x2D
0x66, 0x0C
0x67, 0x38
0x66, 0x0D
0x67, 0x03
0x66, 0x0A
0x67, 0x20
0x66, 0x0B
0x67, 0x02
0x66, 0x0E
0x67, 0x03
0x64, (1 << 2) | (1 << 1) // color pattern + gen pattern
0x01, 0x00

Hello Max,

if you can use our ALP GUI that would make it much easier for you to enable Pattgen or any other functions.

Unfortunately I can't because not using EVM board whereas ALP GUI tool does not saved modified registers. Could you review the settings to see what I am missing?

Are you using the internal default timing configuration or external timing with custome configuration?

Please check the mentioned App Note, section "4.2 Internal Default Timing Configuration" and in section "4.3 Custom Display Configuration".

I am configuring to have internal clock source + own timing and that's why passing others parameters via PGIA & PGID. Am I missing anything?

Basically setting register 0x64 and 0x65 should be sufficient.

I tried it but still having the same results. Table 71. CML_OUTPUT_CTL3 Register Field Descriptions of DS90UB948 datasheet is saying that CML TX must be powered down prior to enabling Pattern Generator. Does it mean that i should set CML_OUTPUT_CTL3.CML_TX_PWDN to 1 before setting PGCTL.PATGEN_EN to 1? 

I tried it but found that after setting CML_TX_PWDN=1, device stops responding over i2c bus.

In pattern gen mode of Ub948, should I expect to see GENERAL_STATUS.LOCK=1?

Hello Max,

Do not configure CML_OUTPUT_CTL3 on the 948 for 941AS PATGEN. You do not need to configure any 948 side registers to achieve 941AS side PATGEN. Also to answer your question, when 948 is the one generating the pattern, then you will not see LOCK between the 941AS and the 948 (if the 948 is using internally generated clock). 

For your 941AS PATGEN configuration, please provide the intended video parameters for your display including the following:

PCLK Rate = 

Htotal = 

Hactive = 

HFP = 

HSYNC = 

HBP = 

Vtotal = 

Vactive = 

VFP = 

VSYNC = 

VBP = 

Hsync Polarity = 

Vsync Polarity = 

Best Regards,

Casey 

Hi Casey,

Thanks, here it goes info for dual lvds panel (1920x720 - DE mode):

clk freq = 45.6
horizontal display area = 960
horizontal pulse width = 18
horizontal back proch = 50
horizontal front porch = 14
vertical display = 720
vertical pulse width = 1
vertical back porch = 4
vertical front porch = 4

Thanks. I think UB947 is typo. I should be using UB941 here. Am I right?

I have tried this script but panel does not show anything. It remains blank. Am I missing anything?

Hello Max,

Are you using ALP? Can you share the Information Tab screenshot after you have run this script?

Best Regards,

Casey 

Nope I am working with prototype hardware.

Regards,

Hello Max, 

You can still link ALP to prototype HW which may be useful to help you debug this issue further. If you have Aardvark or USB2ANY, you can connect the I2C lines to the target board and then connect via USB to your PC. Then you should be able to access 941AS through the GUI to help check registers, configurations, etc. quickly. Is this something you have the capability to utilize?

Best Regards,

Casey