Dear Sir
Our plotform is Xilinx Zynq SoC, we use DP83460 as PL Ethernet.
We have two project, Xilinx Zynq 7000(XC7Z020) and Zynq UltraScale+(XCZU3EG).
Xilinx Zynq 7000(XC7Z020) work fine.(PL Ethernet with DP83460).
But Xilinx Zynq UltraScale+(XCZU3EG) (PL Ethernet with DP83460) doesn't work!
We had checked the following items
1) Power (3.3V, 0V) => OK
2) CRYSTAL/OSCILLATOR INPUT (X1) (25MHz) => OK
3) Signal
- RESET => high(3.14V)
- MDIO, MDC => high(3.3V) ... not knowing if it is OK for register configuration
- (TX CLK, TX EN) = (50MHz, 750mV) ... where Xilinx Zynq 7000(XC7Z020) work fine at (25MHz, 50mV)
- (RX CLK, RX DV) = (50MHz, 50mV) ... where Xilinx Zynq 7000(XC7Z020) work fine at (25MHz, 50mV)
Is there any suggestion to solve the Xilinx Zynq UltraScale+(XCZU3EG) (PL Ethernet with DP83460) problem ?
