Hi,
I am debugging a case where questions came up for Xio2001.
Do you know if there is a minimum time that the SERR# signal needs to be low, to be properly recognised by the bridge?
Kind regards,
Marion
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Hi,
I am debugging a case where questions came up for Xio2001.
Do you know if there is a minimum time that the SERR# signal needs to be low, to be properly recognised by the bridge?
Kind regards,
Marion
Hi Marion,
Sorry for the delay. The minimum time for PCI shared signals like SERR# to be recognized will mainly be limited by the PCI clock speed.
On page 21 of the datasheet, there are a few parameters related to signal timing. Assuming the PCI clock speed is 33MHz, the SERR# signal setup time is 7ns. This means the SERR# signal needs to be stable for 7ns before the rising edge of the PCI clock. The clock in this example has a period of 30.3ns between each rising edge, so the worst-case scenario would be ~40ns.
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