• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 303 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO2001: minimum time that the SERR# signal needs to be low

Marion Loessl
Expert 3705 points
Part Number: XIO2001

Hi,

I am debugging a case where questions came up for Xio2001.

Do you know if there is a minimum time that the SERR# signal needs to be low, to be properly recognised by the bridge?

Kind regards,

Marion

  • 0
    TI__Mastermind 27925 points

    Hi Marion,

    Sorry for the delay.  The minimum time for PCI shared signals like SERR# to be recognized will mainly be limited by the PCI clock speed.

    On page 21 of the datasheet, there are a few parameters related to signal timing.  Assuming the PCI clock speed is 33MHz, the SERR# signal setup time is 7ns.  This means the SERR# signal needs to be stable for 7ns before the rising edge of the PCI clock.  The clock in this example has a period of 30.3ns between each rising edge, so the worst-case scenario would be ~40ns.

  • 0 in reply to Nicholaus_Malone
    TI__Mastermind 27925 points

    This issue is now being handled directly over e-mail to protect confidential information.  Marking this question as resolved.