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DP83867IR: RGMII CLT&DCTL Register Default values

megumi.u
Prodigy 40 points
Part Number: DP83867IR


Hello,

I designed and manufactured the board using DP83867 IRPAP in January 2019.

However, the same board manufactured in May 2020 could not receive 1000BASE packets.

Immediately after the reset, when I checked the default values of registers 0x0032 and 0x0086 with MDIO, they were the values below, which was different from the data sheet.

・ Board manufactured on 2019/010

x0032: 0x00D10

x0086: 0x007F

・ Board manufactured on 2020/05

0x0032: 0x00D2

0x0086: 0x007F

・ Default value of data sheet

0x0032: 0x00D0 (RGMII ENABLE)

0x0086: 0x0077

Communication was restored by resetting the delay value of RXCLK.

With the exception of RGMII enable and TX skew, these registers should have no strap settings on the PAP, but what causes the default values to fluctuate?

  • 0
    TI__Expert 7040 points

    Hello,

    Can you please clarify the register value of 0x0032 in the 10/2019 batch?

    Can you also please provide the register values of 0x006E and 0x006F?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 40 points

    Hi Justin,

    Sorry,Correct the register value of 2019/01.

    0x0032: 0x00D1

    Provides the confirmed 0x006E and 0x006F register values.
    These were the same value in both lots.

    ・ Board manufactured on 2019/01

    0x006E: 0x0000

    0x006F: 0x0104

    ・ Board manufactured on 2020/05

    0x006E: 0x0000

    0x006F: 0x0104

    The circuit has a strap configuration of MODE4 for RX_DV and MODE1 for the others.
    I think the strap settings are reflected correctly, but some reserve values for 0x006F differ from the default values in the datasheet.
    Megumi

  • 0 in reply to megumi.u
    TI__Expert 7040 points

    Hi Megumi,

    The default values of these registers are difficult to predict because their populated based on the strap settings of the PHY. 

    I will have to follow up with our team to understand if there is some external bootstrapping that is setting the default values of 0x0032: 0x00D1 and 0x0086: 0x007F. 

    The difference between the default values of the PHY would not explain why the value changed between board manufacture dates however. Are there external connections to the strapping pins listed in the datasheet that could affect the bootstrap voltage seen by the PHY during power-on?

    Because of the holiday season, I expect it will take longer to confirm this information, I'll aim to provide feedback by 11/17.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 40 points
    Dear Justin


    The strap pin is connected to a MAC device (Intel, MAX10) or LED.

    The pin that plays the role of GMII is connected to the MAX10 and is set to the tri-state when the PHY is powered on.
    The control pin of the LED is connected to GND via the LED and a resistor.
    Regards,
    Megumi
  • 0 in reply to megumi.u
    TI__Expert 7040 points

    Hi Megumi,

    Can you please provide the schematic for this application?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 40 points

    Dear Justin

    The circuit around the PHY is attached.
    Unfortunately, we cannot provide all the circuits.

    Regards,

    Megumi

  • 0 in reply to megumi.u
    TI__Expert 7040 points

    Thank you Megumi,

    I will get back with information from our validation team in 1-2 days.

    Regards,
    Justin