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DP83867CR: Link-up issue with 100Mbps cable

Naman Thaker
Prodigy 210 points

Part Number: DP83867CR

Hello,
I am using a IMX8MM based custom boards with DP83867 Ethernet PHY. When I connect the device with Juniper Switch EX3300 using a 100Mbps cable, the link-up does not occur automatically.
When I connect the device with switch using 1Gbps cable, the link-up occurs automatically.
The only way to link-up the device is to run the ethtool command mentioned in below table.
## Cable Link-partner Link-up Remarks
1 1Gbps Straight Cable PC Pass Static IP assigned on both sides i.e. PC and IMX8MM board.
2 1Gbps Cross Cable PC Pass Static IP assigned on both sides i.e. PC and IMX8MM board.
3 100Mbps Straight Cable PC Fail Static IP assigned on both sides.
Need to run below commands for link-up
PC: sudo ethtool -s eno1 speed 100 duplex full autoneg off
IMX8MM: ethtool -s eth0 speed 100 duplex full autoneg off
4 100Mbps Straight Cable 100Mbps Router Pass Static IP assigned on both sides i.e. PC and IMX8MM board.
Connection detail :
DP83867 -> 100Mbps cable -> 100Mbps router
PC -> 1Gbps cable -> 100Mbps router
5 1Gbps Straight Cable 100Mbps Router Pass Static IP assigned on both sides.
Connection detail :
DP83867 -> 1Gbps cable -> 100Mbps router
PC -> 1Gbps cable -> 100Mbps router
6 1Gbps Straight Cable Juniper EX3300 Switch Pass Dynamic IP assigned on both devices.
Connection detail :
DP83867 -> 1Gbps cable -> Juniper EX3300 Switch
PC -> 1Gbps cable -> Juniper EX3300 Switch
7 100Mbps Straight Cable Juniper EX3300 Switch Fail Dynamic IP assigned on both devices.
Connection detail :
DP83867 -> 100Mbps cable -> Juniper EX3300 Switch
PC -> 1Gbps cable -> Juniper EX3300 Switch
Need to run below command on IMX8MM device for link-up
ethtool -s eth0 speed 100 duplex full
I tested the same with IMX8MM EVK which has Qualcomm AR8031 PHY and same IMX8MM processor, but in that such issues are not observed. The link-up occurs automatically on IMX8MM EVK. Based on this I suspect that the issue is PHY specific.

Please let me know your feedback on our observation. Let me know if you need any other detail.
Thanks,
Naman
  • 0
    TI__Expert 7040 points

    Hi Naman,

    The PHY may be completing auto-negotiation on channel A of the 100M cable, where both the DUT and Link Partner advertise 1G speeds, and auto-negotiation resolves to 1G mode. However, due to the 100M cable not having connections on channels C & D, the PHY drops link and enters this stuck state. 

    You can enable the Speed Optimization feature of the DP83867 to avoid this stalemate after a certain number of link-ups. Section 8.4.6.5 of the DP83867 datasheet discusses this feature and register 0x0014 can be used to enable the feature.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    I tried enabling the Speed Optimization feature of DP83867 but the issue still persists. Let me know if there are any other features that might help.

    Regards,

    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    In the failing tests, you can disable the advertisement of 1000Mbps capabilities of the DP83867 in register 0x0009[9:8]. If you do this and restart auto-negotiation, do you still see the failures?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    When I restart the auto-negotiation after disabling advertisement of 1000Mbps, it automatically re-enables advertisement of 1000Mbps.
    If I keep advertisement of 1000Mbps disabled and connect the 100Mbps cable then the issue persists. The moment I restart auto-negotiation, the 9th bit of 0x0009 gets set i.e. advertisement of 1000Mbps is enabled.
    I used phytool app to change the register setting.
    phytool write eth0/0:0/0x0009 0x0000

    When I read back the register I get 0x0000 value (default is 0x0200). After restarting auto-negotiation it is set to 0x0200.

    Command to restart auto-negotiation:
    ethtool -s eth0 autoneg off && ethtool -s eth0 autoneg on

    Let me know if there is some other method to test this.
    I assume I will need to make changes in the kernel driver to perform this test. If my assumption is correct, then please suggest me the changes that would be required to test.

    Regards,
    Naman Thaker

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    I do not know the specifics of hte ethtool autoneg off/on commands, but I suspect it issues are hard reset to the PHY. 

    You could change the register settings and then issue a software restart through the register commands below:

    phytool write eth0/0:0/0x0009 0x0000

    phytool write eth0/0:0/0x001F 0x4000

    A software restart will restart the PHY without resetting changes made to internal registers. 

    Can you also share the register commands used to test the speed optimization feature? 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    After issuing software restart using below commands as you suggested, the link is detected and IP is also assigned to the device:
    phytool write eth0/0:0/0x0009 0x0000
    phytool write eth0/0:0/0x001F 0x4000

    But since 1Gbps is not being advertised, only 100Mbps speed is achieved even when using a 1Gbps cable and link partner. But with 100Mbps cable, the link is successfully detected and ~100Mbps speed is also achieved.

    The command I used to test speed optimization feature is as below:
    phytool write eth0/0:0/0x0014 0x2fc7

    I also added below piece of code in the DP83867 driver so that the speed optimization register will be initialized with the fixed value.
    ret = phy_write(phydev, 0x14, 0x2fc7);                              
    if (ret)                                                            
            return ret;

    Regards,
    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    Thank you. Can you also confirm that a software restart is done after enabling speed optimization through registers?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    I tried to perform a software restart after enabling speed optimization using below commands, but the link was not detected.
    phytool write eth0/0:0/0x0014 0x2fc7
    phytool write eth0/0:0/0x001F 0x4000

    Regards,
    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    With the speed optimization enabled, it can take up to 45 seconds before the PHY will downshift speeds to 100M. Can you confirm there is sufficient time to let the PHY resolve the speed optimization? 

    You can reduce the number of attempts to link at 1G before the downshift to reduce the link time in register 0x0014 as well.

    Regards,

    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    With speed optimization enabled, the link gets detected after 30-45 seconds. But speed does not downshift to 100Mbps, instead it remains at 1000MBps. Also, the device does not get IP address even after 5 mins.

    Ethtool output after 5mins:
    $ ./ethtool eth0                                                                                                     
    Settings for eth0:
        Supported ports: [ TP MII ]
        Supported link modes:   10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
        Supported pause frame use: Symmetric
        Supports auto-negotiation: Yes
        Advertised link modes:  10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
        Advertised pause frame use: Symmetric
        Advertised auto-negotiation: Yes
        Link partner advertised link modes:  10baseT/Half 10baseT/Full
                                             100baseT/Half 100baseT/Full
                                             1000baseT/Full
        Link partner advertised pause frame use: Symmetric
        Link partner advertised auto-negotiation: Yes
        Speed: 1000Mb/s
        Duplex: Full
        Port: MII
        PHYAD: 0
        Transceiver: external
        Auto-negotiation: on
        Supports Wake-on: g
        Wake-on: d
        Link detected: yes


    Same thing is observed with reduced link time.

    Regards,
    Naman

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    Could you please suggest some other debugging points?

    Regards,
    Naman Thaker

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    Can you please provide the register information of register 0x0000-0x001F when the PHY is linked after speed optimization is completed? Can you also confirm that the 100M straight cable is a 4 wire cable connected to channels A & B of the PHY?

    The PHY should not be linked in 1G mode when a 4 wire cable is connected to the MDI, I am hoping the register information will shed light as to what is happening. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Expert 7040 points

    Hi Naman,

    Can you also probe the RX_CLK pin to determine the speed that is being communicated to the MAC interface?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    Below are the register information when the PHY is linked after speed optimization:

    REG=0x0, VAL=0x1140                                                             
    REG=0x1, VAL=0x796d                                                             
    REG=0x2, VAL=0x2000                                                             
    REG=0x3, VAL=0xa231                                                             
    REG=0x4, VAL=0x05e1                                                             
    REG=0x5, VAL=0xc5e1                                                             
    REG=0x6, VAL=0x006d                                                             
    REG=0x7, VAL=0x2001                                                             
    REG=0x8, VAL=0x49f1                                                             
    REG=0x9, VAL=0x0200                                                             
    REG=0xa, VAL=0x0800                                                             
    REG=0xb, VAL=0000                                                               
    REG=0xc, VAL=0000                                                               
    REG=0xd, VAL=0x401f                                                             
    REG=0xe, VAL=0x0077                                                             
    REG=0xf, VAL=0x3000                                                             
    REG=0x10, VAL=0x5048                                                            
    REG=0x11, VAL=0x6f02                                                            
    REG=0x12, VAL=0000                                                              
    REG=0x13, VAL=0x0004                                                            
    REG=0x14, VAL=0x2fc7                                                            
    REG=0x15, VAL=0000                                                              
    REG=0x16, VAL=0000                                                              
    REG=0x17, VAL=0x0040                                                            
    REG=0x18, VAL=0x6150                                                            
    REG=0x19, VAL=0x4444                                                            
    REG=0x1a, VAL=0x0002                                                            
    REG=0x1b, VAL=0000                                                              
    REG=0x1c, VAL=0000                                                              
    REG=0x1d, VAL=0000                                                              
    REG=0x1e, VAL=0x0002                                                            
    REG=0x1f, VAL=0000

    And yes, in 100M straight cable Tx-Rx of total 4 channel are connected and it is from Channel A(+A/-A) and Channel B (+B/-B) pairs.

    The RX_CLK is measured to be 25Mhz:

    Regards,

    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    The PHY is showing that it is linked in 100Mbps mode. Register 0x0011[15:14] = 01, meaning the 100Mbps link is established. 

    So there seems to be a disconnect between the PHY link speed and what is reported by the ethtool. Can you provide more information how you are using the ethtool? Do you use the DP83867 Linux driver provided by TI?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    I am using the DP83867 driver available in open source Linux kernel v4.14.98. This driver is readily available in the Android Pie (9.0.0) source for the IMX8M Mini EVK board.
    Please refer below attached driver which was readily available our Android Linux kernel:

    Fullscreen dp83867.c Download 
    /*
 * Driver for the Texas Instruments DP83867 PHY
 *
 * Copyright (C) 2015 Texas Instruments Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/ethtool.h>
#include <linux/kernel.h>
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>

#include <dt-bindings/net/ti-dp83867.h>

#define DP83867_PHY_ID		0x2000a231
#define DP83867_DEVADDR		0x1f

#define MII_DP83867_PHYCTRL	0x10
#define MII_DP83867_MICR	0x12
#define MII_DP83867_ISR		0x13
#define DP83867_CTRL		0x1f
#define DP83867_CFG3		0x1e

/* Extended Registers */
#define DP83867_CFG4            0x0031
#define DP83867_RGMIICTL	0x0032
#define DP83867_STRAP_STS1	0x006E
#define DP83867_RGMIIDCTL	0x0086
#define DP83867_IO_MUX_CFG	0x0170

#define DP83867_SW_RESET	BIT(15)
#define DP83867_SW_RESTART	BIT(14)

/* MICR Interrupt bits */
#define MII_DP83867_MICR_AN_ERR_INT_EN		BIT(15)
#define MII_DP83867_MICR_SPEED_CHNG_INT_EN	BIT(14)
#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN	BIT(13)
#define MII_DP83867_MICR_PAGE_RXD_INT_EN	BIT(12)
#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN	BIT(11)
#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN	BIT(10)
#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN	BIT(8)
#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN	BIT(4)
#define MII_DP83867_MICR_WOL_INT_EN		BIT(3)
#define MII_DP83867_MICR_XGMII_ERR_INT_EN	BIT(2)
#define MII_DP83867_MICR_POL_CHNG_INT_EN	BIT(1)
#define MII_DP83867_MICR_JABBER_INT_EN		BIT(0)

/* RGMIICTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
#define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)

/* STRAP_STS1 bits */
#define DP83867_STRAP_STS1_RESERVED		BIT(11)

/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
#define DP83867_PHYCR_FIFO_DEPTH_MASK		(3 << 14)
#define DP83867_PHYCR_RESERVED_MASK		BIT(11)

/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4

/* IO_MUX_CFG bits */
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL	0x1f

#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f

/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)

enum {
	DP83867_PORT_MIRROING_KEEP,
	DP83867_PORT_MIRROING_EN,
	DP83867_PORT_MIRROING_DIS,
};

struct dp83867_private {
	int rx_id_delay;
	int tx_id_delay;
	int fifo_depth;
	int io_impedance;
	int port_mirroring;
	bool rxctrl_strap_quirk;
};

static int dp83867_ack_interrupt(struct phy_device *phydev)
{
	int err = phy_read(phydev, MII_DP83867_ISR);

	if (err < 0)
		return err;

	return 0;
}

static int dp83867_config_intr(struct phy_device *phydev)
{
	int micr_status;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
		micr_status = phy_read(phydev, MII_DP83867_MICR);
		if (micr_status < 0)
			return micr_status;

		micr_status |=
			(MII_DP83867_MICR_AN_ERR_INT_EN |
			MII_DP83867_MICR_SPEED_CHNG_INT_EN |
			MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
			MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
			MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
			MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);

		return phy_write(phydev, MII_DP83867_MICR, micr_status);
	}

	micr_status = 0x0;
	return phy_write(phydev, MII_DP83867_MICR, micr_status);
}

static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
	struct dp83867_private *dp83867 =
		(struct dp83867_private *)phydev->priv;
	u16 val;

	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);

	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
		val |= DP83867_CFG4_PORT_MIRROR_EN;
	else
		val &= ~DP83867_CFG4_PORT_MIRROR_EN;

	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);

	return 0;
}

#ifdef CONFIG_OF_MDIO
static int dp83867_of_init(struct phy_device *phydev)
{
	struct dp83867_private *dp83867 = phydev->priv;
	struct device *dev = &phydev->mdio.dev;
	struct device_node *of_node = dev->of_node;
	int ret;

	if (!of_node)
		return -ENODEV;

	dp83867->io_impedance = -EINVAL;

	/* Optional configuration */
	if (of_property_read_bool(of_node, "ti,max-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;

	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
					"ti,dp83867-rxctrl-strap-quirk");

	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
				   &dp83867->rx_id_delay);
	if (ret &&
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
	     phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
		return ret;

	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
				   &dp83867->tx_id_delay);
	if (ret &&
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
	     phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
		return ret;

	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
		dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;

	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
		dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;

	return of_property_read_u32(of_node, "ti,fifo-depth",
				   &dp83867->fifo_depth);
}
#else
static int dp83867_of_init(struct phy_device *phydev)
{
	return 0;
}
#endif /* CONFIG_OF_MDIO */

static int dp83867_config_init(struct phy_device *phydev)
{
	struct dp83867_private *dp83867;
	int ret, val, bs;
	u16 delay;

	if (!phydev->priv) {
		dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
				       GFP_KERNEL);
		if (!dp83867)
			return -ENOMEM;

		phydev->priv = dp83867;
		ret = dp83867_of_init(phydev);
		if (ret)
			return ret;
	} else {
		dp83867 = (struct dp83867_private *)phydev->priv;
	}

	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
	if (dp83867->rxctrl_strap_quirk) {
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
		val &= ~BIT(7);
		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
	}

	if (phy_interface_is_rgmii(phydev)) {
		val = phy_read(phydev, MII_DP83867_PHYCTRL);
		if (val < 0)
			return val;
		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);

		/* The code below checks if "port mirroring" N/A MODE4 has been
		 * enabled during power on bootstrap.
		 *
		 * Such N/A mode enabled by mistake can put PHY IC in some
		 * internal testing mode and disable RGMII transmission.
		 *
		 * In this particular case one needs to check STRAP_STS1
		 * register's bit 11 (marked as RESERVED).
		 */

		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
		if (bs & DP83867_STRAP_STS1_RESERVED)
			val &= ~DP83867_PHYCR_RESERVED_MASK;

		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
		if (ret)
			return ret;
	}

	if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
	    (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
			val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
			val |= DP83867_RGMII_TX_CLK_DELAY_EN;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
			val |= DP83867_RGMII_RX_CLK_DELAY_EN;

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);

		delay = (dp83867->rx_id_delay |
			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
			      delay);

		if (dp83867->io_impedance >= 0) {
			val = phy_read_mmd(phydev, DP83867_DEVADDR,
					   DP83867_IO_MUX_CFG);

			val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
			val |= dp83867->io_impedance &
			       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;

			phy_write_mmd(phydev, DP83867_DEVADDR,
				      DP83867_IO_MUX_CFG, val);
		}
	}

	/* Enable Interrupt output INT_OE in CFG3 register */
	if (phy_interrupt_is_valid(phydev)) {
		val = phy_read(phydev, DP83867_CFG3);
		val |= BIT(7);
		phy_write(phydev, DP83867_CFG3, val);
	}

	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
		dp83867_config_port_mirroring(phydev);

	return 0;
}

static int dp83867_phy_reset(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
	if (err < 0)
		return err;

	return dp83867_config_init(phydev);
}

static struct phy_driver dp83867_driver[] = {
	{
		.phy_id		= DP83867_PHY_ID,
		.phy_id_mask	= 0xfffffff0,
		.name		= "TI DP83867",
		.features	= PHY_GBIT_FEATURES,
		.flags		= PHY_HAS_INTERRUPT,

		.config_init	= dp83867_config_init,
		.soft_reset	= dp83867_phy_reset,

		/* IRQ related */
		.ack_interrupt	= dp83867_ack_interrupt,
		.config_intr	= dp83867_config_intr,

		.config_aneg	= genphy_config_aneg,
		.read_status	= genphy_read_status,
		.suspend	= genphy_suspend,
		.resume		= genphy_resume,
	},
};
module_phy_driver(dp83867_driver);

static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
	{ DP83867_PHY_ID, 0xfffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, dp83867_tbl);

MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
MODULE_LICENSE("GPL");



    We are using the open source Ethtool which is a standard utility for displaying and modifying network interface controller and their device drivers.
    The Ethtool (v4.17) has been cross-compiled for Andoird architecture.
    https://mirrors.edge.kernel.org/pub/software/network/ethtool/

    When we run Ethtool as below is displays various parameters that I have previously shared.
    # ethtool eth0

    Here eth0 is the Ethernet interface used in our device.

    I am also attaching here the register settings and Ethtool output obtained in different cases.

    Fullscreen register_settings_ethtool_output.txt Download 
    ========================================================================
WHEN DEVICE IS NOT CONNECTED OVER ETHERNET
========================================================================
REG=0x0, VAL=0x1140                                                             
REG=0x1, VAL=0x7949                                                             
REG=0x2, VAL=0x2000                                                             
REG=0x3, VAL=0xa231                                                             
REG=0x4, VAL=0x05e1                                                             
REG=0x5, VAL=0000                                                               
REG=0x6, VAL=0x0064                                                             
REG=0x7, VAL=0x2001                                                             
REG=0x8, VAL=0000                                                               
REG=0x9, VAL=0x0200                                                             
REG=0xa, VAL=0000                                                               
REG=0xb, VAL=0000                                                               
REG=0xc, VAL=0000                                                               
REG=0xd, VAL=0x401f                                                             
REG=0xe, VAL=0x0077                                                             
REG=0xf, VAL=0x3000                                                             
REG=0x10, VAL=0x5048                                                            
REG=0x11, VAL=0x0002                                                            
REG=0x12, VAL=0000                                                              
REG=0x13, VAL=0x0040                                                            
REG=0x14, VAL=0x29c7                                                            
REG=0x15, VAL=0000                                                              
REG=0x16, VAL=0000                                                              
REG=0x17, VAL=0x0040                                                            
REG=0x18, VAL=0x6150                                                            
REG=0x19, VAL=0x4444                                                            
REG=0x1a, VAL=0x0002                                                            
REG=0x1b, VAL=0000                                                              
REG=0x1c, VAL=0000                                                              
REG=0x1d, VAL=0000                                                              
REG=0x1e, VAL=0x0002                                                            
REG=0x1f, VAL=0000                                                              
evk_8mm:/ # ethtool eth0                                                        
Settings for eth0:                                                              
        Supported ports: [ TP MII ]                                             
        Supported link modes:   10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Supported pause frame use: Symmetric                                    
        Supports auto-negotiation: Yes                                          
        Advertised link modes:  10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Advertised pause frame use: Symmetric                                   
        Advertised auto-negotiation: Yes                                        
        Speed: 10Mb/s                                                           
        Duplex: Half                                                            
        Port: MII                                                               
        PHYAD: 0                                                                
        Transceiver: external                                                   
        Auto-negotiation: on                                                    
        Supports Wake-on: g                                                     
        Wake-on: d                                                              
        Link detected: no                                                       


========================================================================
WHEN 1GBPS CABLE IS CONNECTED TO DEVICE
========================================================================
REG=0x0, VAL=0x1140                                                             
REG=0x1, VAL=0x796d                                                             
REG=0x2, VAL=0x2000                                                             
REG=0x3, VAL=0xa231                                                             
REG=0x4, VAL=0x05e1                                                             
REG=0x5, VAL=0xc5e1                                                             
REG=0x6, VAL=0x006f                                                             
REG=0x7, VAL=0x2001                                                             
REG=0x8, VAL=0x6801                                                             
REG=0x9, VAL=0x0200                                                             
REG=0xa, VAL=0x3800                                                             
REG=0xb, VAL=0000                                                               
REG=0xc, VAL=0000                                                               
REG=0xd, VAL=0x401f                                                             
REG=0xe, VAL=0x0077                                                             
REG=0xf, VAL=0x3000                                                             
REG=0x10, VAL=0x5048                                                            
REG=0x11, VAL=0xbf02                                                            
REG=0x12, VAL=0000                                                              
REG=0x13, VAL=0x1c40                                                            
REG=0x14, VAL=0x29c7                                                            
REG=0x15, VAL=0000                                                              
REG=0x16, VAL=0000                                                              
REG=0x17, VAL=0x0040                                                            
REG=0x18, VAL=0x6150                                                            
REG=0x19, VAL=0x4444                                                            
REG=0x1a, VAL=0x0002                                                            
REG=0x1b, VAL=0000                                                              
REG=0x1c, VAL=0000                                                              
REG=0x1d, VAL=0000                                                              
REG=0x1e, VAL=0x0002                                                            
REG=0x1f, VAL=0000                                                              
evk_8mm:/ # ethtool eth0                                                        
Settings for eth0:                                                              
        Supported ports: [ TP MII ]                                             
        Supported link modes:   10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Supported pause frame use: Symmetric                                    
        Supports auto-negotiation: Yes                                          
        Advertised link modes:  10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Advertised pause frame use: Symmetric                                   
        Advertised auto-negotiation: Yes                                        
        Link partner advertised link modes:  10baseT/Half 10baseT/Full          
                                             100baseT/Half 100baseT/Full        
                                             1000baseT/Full                     
        Link partner advertised pause frame use: Symmetric                      
        Link partner advertised auto-negotiation: Yes                           
        Speed: 1000Mb/s                                                         
        Duplex: Full                                                            
        Port: MII                                                               
        PHYAD: 0                                                                
        Transceiver: external                                                   
        Auto-negotiation: on                                                    
        Supports Wake-on: g                                                     
        Wake-on: d                                                              
        Link detected: yes                                                      



========================================================================
WHEN 100MBPS CABLE IS CONNECTED
========================================================================
REG=0x0, VAL=0x1140                                                             
REG=0x1, VAL=0x7949                                                             
REG=0x2, VAL=0x2000                                                             
REG=0x3, VAL=0xa231                                                             
REG=0x4, VAL=0x05e1                                                             
REG=0x5, VAL=0xc5e1                                                             
REG=0x6, VAL=0x006f                                                             
REG=0x7, VAL=0x2001                                                             
REG=0x8, VAL=0x6801                                                             
REG=0x9, VAL=0x0200                                                             
REG=0xa, VAL=0x0800                                                             
REG=0xb, VAL=0000                                                               
REG=0xc, VAL=0000                                                               
REG=0xd, VAL=0x401f                                                             
REG=0xe, VAL=0x0077                                                             
REG=0xf, VAL=0x3000                                                             
REG=0x10, VAL=0x5048                                                            
REG=0x11, VAL=0xb002                                                            
REG=0x12, VAL=0000                                                              
REG=0x13, VAL=0x95c6                                                            
REG=0x14, VAL=0x29c7                                                            
REG=0x15, VAL=0000                                                              
REG=0x16, VAL=0000                                                              
REG=0x17, VAL=0x0040                                                            
REG=0x18, VAL=0x6150                                                            
REG=0x19, VAL=0x4444                                                            
REG=0x1a, VAL=0x0002                                                            
REG=0x1b, VAL=0000                                                              
REG=0x1c, VAL=0000                                                              
REG=0x1d, VAL=0000                                                              
REG=0x1e, VAL=0x0002                                                            
REG=0x1f, VAL=0000                                                              
evk_8mm:/ # ethtool eth0                                                        
Settings for eth0:                                                              
        Supported ports: [ TP MII ]                                             
        Supported link modes:   10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Supported pause frame use: Symmetric                                    
        Supports auto-negotiation: Yes                                          
        Advertised link modes:  10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Advertised pause frame use: Symmetric                                   
        Advertised auto-negotiation: Yes                                        
        Link partner advertised link modes:  10baseT/Half 10baseT/Full          
                                             100baseT/Half 100baseT/Full        
                                             1000baseT/Full                     
        Link partner advertised pause frame use: Symmetric                      
        Link partner advertised auto-negotiation: Yes                           
        Speed: 1000Mb/s                                                         
        Duplex: Full                                                            
        Port: MII                                                               
        PHYAD: 0                                                                
        Transceiver: external                                                   
        Auto-negotiation: on                                                    
        Supports Wake-on: g                                                     
        Wake-on: d                                                              
        Link detected: no                                                       

========================================================================
WHEN 1GBPS CABLE IS CONNECTED + SPEED OPTIMIZATION
========================================================================
REG=0x0, VAL=0x1140                                                             
REG=0x1, VAL=0x796d                                                             
REG=0x2, VAL=0x2000                                                             
REG=0x3, VAL=0xa231                                                             
REG=0x4, VAL=0x05e1                                                             
REG=0x5, VAL=0xc5e1                                                             
REG=0x6, VAL=0x006d                                                             
REG=0x7, VAL=0x2001                                                             
REG=0x8, VAL=0x49f1                                                             
REG=0x9, VAL=0x0200                                                             
REG=0xa, VAL=0x0800                                                             
REG=0xb, VAL=0000                                                               
REG=0xc, VAL=0000                                                               
REG=0xd, VAL=0x401f                                                             
REG=0xe, VAL=0x0077                                                             
REG=0xf, VAL=0x3000                                                             
REG=0x10, VAL=0x5048                                                            
REG=0x11, VAL=0x6f02                                                            
REG=0x12, VAL=0000                                                              
REG=0x13, VAL=0x0004                                                            
REG=0x14, VAL=0x2fc7                                                            
REG=0x15, VAL=0000                                                              
REG=0x16, VAL=0000                                                              
REG=0x17, VAL=0x0040                                                            
REG=0x18, VAL=0x6150                                                            
REG=0x19, VAL=0x4444                                                            
REG=0x1a, VAL=0x0002                                                            
REG=0x1b, VAL=0000                                                              
REG=0x1c, VAL=0000                                                              
REG=0x1d, VAL=0000                                                              
REG=0x1e, VAL=0x0002                                                            
REG=0x1f, VAL=0000                                                              
evk_8mm:/ # ethtool eth0                                                        
Settings for eth0:                                                              
        Supported ports: [ TP MII ]                                             
        Supported link modes:   10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Supported pause frame use: Symmetric                                    
        Supports auto-negotiation: Yes                                          
        Advertised link modes:  10baseT/Half 10baseT/Full                       
                                100baseT/Half 100baseT/Full                     
                                1000baseT/Full                                  
        Advertised pause frame use: Symmetric                                   
        Advertised auto-negotiation: Yes                                        
        Link partner advertised link modes:  10baseT/Half 10baseT/Full          
                                             100baseT/Half 100baseT/Full        
                                             1000baseT/Full                     
        Link partner advertised pause frame use: Symmetric                      
        Link partner advertised auto-negotiation: Yes                           
        Speed: 1000Mb/s                                                         
        Duplex: Full                                                            
        Port: MII                                                               
        PHYAD: 0                                                                
        Transceiver: external                                                   
        Auto-negotiation: on                                                    
        Supports Wake-on: g                                                     
        Wake-on: d                                                              
        Link detected: yes


    Regards,
    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    I will review the Linux driver with our driver expert to assess what could be causing the mismatch between the ethtool and PHY registers. Please allow 2-3 days for my feedback.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Expert 7040 points

    Hi Naman,

    There is an upstream driver that has enabled speed optimization feature in the driver. You can use this driver to implement or back port the patch in the link below:

    https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/net/phy/dp83867.c?id=cd26d72d4d43175cec8c10bed4df7f21ac5316b3

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    Could you test the old driver at your end and try to reproduce the issue and then check if the issue is resolved with the new driver?
    Please note our issue is not observed with every router but with specific one like EX3000 in our case.

    Unfortunately, right now we do not the time to back-port the patch/driver in our system as we are very close to production. Next year we plan to update our release to latest one, in which we feel that this issue could be resolved.
    Could you please check and confirm if the new driver works? If it does, we will switch to the new kernel itself.

    Regards,
    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    I cannot check the driver on the specific router you are referencing. I do not have access to off the shelf switches and would likely 3-4 weeks before I can test the setup you requested.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 210 points

    Hi Justin,

    Could you share to us two evaluation kits, one with current Kernel V4.14 in which we observe the issue and second one with new kernel with the updated driver for speed optimization? Then we can test them here and check whether the new driver works.

    Regards,
    Naman

  • 0 in reply to Naman Thaker
    TI__Expert 7040 points

    Hi Naman,

    Our DP83867 EVMs do not come with Linux driver's implemented in the EVM, we offer the MAC connection pins and MDC/MDIO access to evaluate the PHY. I don't believe it will be possible to ship EVMs with different kernel's loaded. 

    I've confirmed with our driver developer that the upstream driver is working correctly and is being used in existing applications.

    Specifically, the read_status routine needs to be implemented for the speed and duplex to be read correctly from the PHY_STATUS register. I've highlighted it here in the latest DP83867 driver:

    https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/dp83867.c?h=v5.10-rc7#n313

    Regards,
    Justin