DP83867E: SI analysis error

Hello Jayanth,

I was wondering if you could provide more information so we may better understand your problem. What pins are you connecting in this simulation? What IBIS model are you using for the DP83867? Can you confirm you are using Hyperlynx as the SI analysis tool? Can you describe to me what the system is in your simulation?

Sincerely,

Gerome

Hello Gerome,

Thanks for your reply. As per your questions,

1. We have used SERDES in ethernet interface. MGT pins of FPGA are connected to SGMII pins of PHY transceiver pins.
2. We are IBS AMI model published in DP83867 page from TI website.
3. Yes, We are using Hyperlynx tool for SI analysis
4. I have not understood the last question.

Thanks,

Jayanth

Hi Jayanth,

Our team will take a look at this and will get a response back to you in 2-3 days.

Sincerely,

Gerome

Hello Gerome,

The Same IBIS AMI model is used for simulating Signal integrity between FPGA and SFP+ in my project, I have not faced any issue in simulating it, Keeping this in my mind I feel there is no issue with Xilinx Model, Due to confidentiality agreement I cannot share the file in attachment, But the link I used to download the IBS AMI model for xilinx FPGA is provided below.

For the reference, We are using Xilinx Virtex 7 FPGA (part# XQ7V585T-1RF1761M) in our project and in SI analysis, Same model is used.

Thanks,

Jayanth

Hi Jayanth,

I would check other parts of the setup. We were able to verify the IBIS AMI model is operating correctly, and if you are sure the Xilinx model works as intended, then the problem lies somewhere else.

Sincerely,

Gerome

Hello Gerome,

Can you please share your setup data for simulation or results for that matter. It would help us knowing root cause for the error we got in the tool, if we made any mistake.

Thanks,

Jayanth.

Jayanth,

The team is working on this, and will provide you with an update in 1-2 days.

Sincerely,

Gerome

Hello Gerome,

Sorry for the late reply...

Please find our ffs file uploaded here. In our case the issue is still unresolved, Please check the topology and sch, We are still getting the same error.1rx.zip

Thanks,

Jayanth

Hi Jayanth,

I believe this issue is more suited for Hyperlynx support. We have already verified that our model is not causing the issue you are seeing, and have uploaded an example of a working setup using the same model. I would suggest seeing if there are any setup differences between the two files, but I think Hyperlynx support would be equipped to resolve your issue.

Sincerely,

Gerome